@@ -24,6 +24,58 @@ F: ; preds = %0
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ret void
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}
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+ define void @test_unordered (ptr noalias %b , ptr noalias %c , ptr noalias %Q , ptr noalias %R , i32 %i ) {
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+ ; CHECK-LABEL: @test_unordered(
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+ ; CHECK-NEXT: entry:
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+ ; CHECK-NEXT: [[ldR1:%.*]] = load i32, ptr [[R:%.*]], align 8
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+ ; CHECK-NEXT: switch i32 %i, label %bb0 [
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+ ; CHECK-NEXT: i32 2, label %bb1
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+ ; CHECK-NEXT: i32 3, label %bb2
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+ ; CHECK-NEXT: ]
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+ ; CHECK: common.ret:
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+ ; CHECK-NEXT: ret void
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+ ; CHECK: bb0:
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+ ; CHECK-NEXT: [[ldQ:%.*]] = load i32, ptr [[Q:%.*]], align 8
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+ ; CHECK-NEXT: [[mul:%.*]] = mul i32 [[ldQ:%.*]], 2
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+ ; CHECK-NEXT: [[add:%.*]] = add i32 [[ldR1:%.*]], [[mul:%.*]]
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+ ; CHECK-NEXT: store i32 [[add:%.*]], ptr [[c:%.*]], align 8
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+ ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
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+ ; CHECK: bb1:
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+ ; CHECK-NEXT: store i32 [[ldR1:%.*]], ptr [[c:%.*]], align 4
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+ ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
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+ ; CHECK: bb2:
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+ ; CHECK-NEXT: [[ldQ2:%.*]] = load i32, ptr [[Q:%.*]], align 8
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+ ; CHECK-NEXT: [[sub:%.*]] = sub i32 [[ldR1:%.*]], [[ldQ2:%.*]]
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+ ; CHECK-NEXT: store i32 [[sub:%.*]], ptr [[c:%.*]], align 8
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+ ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
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+
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+ entry:
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+ switch i32 %i , label %bb0 [
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+ i32 2 , label %bb1
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+ i32 3 , label %bb2
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+ ]
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+
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+ bb0: ; preds = %entry
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+ %ldQ1 = load i32 , ptr %Q , align 8
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+ %mul = mul i32 %ldQ1 , 2
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+ %ldR1 = load i32 , ptr %R , align 8
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+ %add = add i32 %ldR1 , %mul
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+ store i32 %add , ptr %c , align 8
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+ ret void
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+
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+ bb1: ; preds = entry
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+ %ldR2 = load i32 , ptr %R , align 8
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+ store i32 %ldR2 , ptr %c
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+ ret void
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+
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+ bb2: ; preds = entry
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+ %ldQ2 = load i32 , ptr %Q , align 8
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+ %ldR3 = load i32 , ptr %R , align 8
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+ %sub = sub i32 %ldR3 , %ldQ2
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+ store i32 %sub , ptr %c , align 8
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+ ret void
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+ }
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+
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define void @test_switch (i64 %i , ptr %Q ) {
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; CHECK-LABEL: @test_switch(
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; CHECK-NEXT: common.ret:
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