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[CodeGen] Clear InitUndef pass new register cache between pass runs
Multiple invocations of the pass could interfere with eachother, preventing some undefs being initialised.
1 parent cd4287b commit 8a0847e

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3 files changed

+75
-74
lines changed

3 files changed

+75
-74
lines changed

‎llvm/lib/CodeGen/InitUndef.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -272,6 +272,7 @@ bool InitUndef::runOnMachineFunction(MachineFunction &MF) {
272272
for (auto *DeadMI : DeadInsts)
273273
DeadMI->eraseFromParent();
274274
DeadInsts.clear();
275+
NewRegs.clear();
275276

276277
return Changed;
277278
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -2474,9 +2474,9 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
24742474
; RV64ZVE32F-NEXT: add a2, a0, a2
24752475
; RV64ZVE32F-NEXT: lw a2, 0(a2)
24762476
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
2477-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2477+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
24782478
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
2479-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
2479+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
24802480
; RV64ZVE32F-NEXT: .LBB35_9: # %else14
24812481
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
24822482
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2519,8 +2519,8 @@ define <8 x i32> @mgather_baseidx_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8 x i1>
25192519
; RV64ZVE32F-NEXT: add a2, a0, a2
25202520
; RV64ZVE32F-NEXT: lw a2, 0(a2)
25212521
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
2522-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2523-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
2522+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
2523+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
25242524
; RV64ZVE32F-NEXT: andi a2, a1, 32
25252525
; RV64ZVE32F-NEXT: bnez a2, .LBB35_8
25262526
; RV64ZVE32F-NEXT: j .LBB35_9
@@ -2624,9 +2624,9 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
26242624
; RV64ZVE32F-NEXT: add a2, a0, a2
26252625
; RV64ZVE32F-NEXT: lw a2, 0(a2)
26262626
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
2627-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2627+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
26282628
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
2629-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
2629+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
26302630
; RV64ZVE32F-NEXT: .LBB36_9: # %else14
26312631
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
26322632
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2669,8 +2669,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
26692669
; RV64ZVE32F-NEXT: add a2, a0, a2
26702670
; RV64ZVE32F-NEXT: lw a2, 0(a2)
26712671
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
2672-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2673-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
2672+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
2673+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
26742674
; RV64ZVE32F-NEXT: andi a2, a1, 32
26752675
; RV64ZVE32F-NEXT: bnez a2, .LBB36_8
26762676
; RV64ZVE32F-NEXT: j .LBB36_9
@@ -2779,9 +2779,9 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
27792779
; RV64ZVE32F-NEXT: add a2, a0, a2
27802780
; RV64ZVE32F-NEXT: lw a2, 0(a2)
27812781
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
2782-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2782+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
27832783
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
2784-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
2784+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
27852785
; RV64ZVE32F-NEXT: .LBB37_9: # %else14
27862786
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
27872787
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2827,8 +2827,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i8_v8i32(ptr %base, <8 x i8> %idxs, <8
28272827
; RV64ZVE32F-NEXT: add a2, a0, a2
28282828
; RV64ZVE32F-NEXT: lw a2, 0(a2)
28292829
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
2830-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2831-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
2830+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
2831+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
28322832
; RV64ZVE32F-NEXT: andi a2, a1, 32
28332833
; RV64ZVE32F-NEXT: bnez a2, .LBB37_8
28342834
; RV64ZVE32F-NEXT: j .LBB37_9
@@ -2936,9 +2936,9 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
29362936
; RV64ZVE32F-NEXT: add a2, a0, a2
29372937
; RV64ZVE32F-NEXT: lw a2, 0(a2)
29382938
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
2939-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2939+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
29402940
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
2941-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
2941+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
29422942
; RV64ZVE32F-NEXT: .LBB38_9: # %else14
29432943
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
29442944
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -2981,8 +2981,8 @@ define <8 x i32> @mgather_baseidx_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <8 x i
29812981
; RV64ZVE32F-NEXT: add a2, a0, a2
29822982
; RV64ZVE32F-NEXT: lw a2, 0(a2)
29832983
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
2984-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
2985-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
2984+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
2985+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
29862986
; RV64ZVE32F-NEXT: andi a2, a1, 32
29872987
; RV64ZVE32F-NEXT: bnez a2, .LBB38_8
29882988
; RV64ZVE32F-NEXT: j .LBB38_9
@@ -3087,9 +3087,9 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
30873087
; RV64ZVE32F-NEXT: add a2, a0, a2
30883088
; RV64ZVE32F-NEXT: lw a2, 0(a2)
30893089
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3090-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
3090+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
30913091
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
3092-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
3092+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
30933093
; RV64ZVE32F-NEXT: .LBB39_9: # %else14
30943094
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
30953095
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -3132,8 +3132,8 @@ define <8 x i32> @mgather_baseidx_sext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
31323132
; RV64ZVE32F-NEXT: add a2, a0, a2
31333133
; RV64ZVE32F-NEXT: lw a2, 0(a2)
31343134
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
3135-
; RV64ZVE32F-NEXT: vmv.s.x v8, a2
3136-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
3135+
; RV64ZVE32F-NEXT: vmv.s.x v12, a2
3136+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
31373137
; RV64ZVE32F-NEXT: andi a2, a1, 32
31383138
; RV64ZVE32F-NEXT: bnez a2, .LBB39_8
31393139
; RV64ZVE32F-NEXT: j .LBB39_9
@@ -3243,9 +3243,9 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
32433243
; RV64ZVE32F-NEXT: add a3, a0, a3
32443244
; RV64ZVE32F-NEXT: lw a3, 0(a3)
32453245
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3246-
; RV64ZVE32F-NEXT: vmv.s.x v8, a3
3246+
; RV64ZVE32F-NEXT: vmv.s.x v12, a3
32473247
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
3248-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
3248+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
32493249
; RV64ZVE32F-NEXT: .LBB40_9: # %else14
32503250
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
32513251
; RV64ZVE32F-NEXT: andi a3, a2, 64
@@ -3291,8 +3291,8 @@ define <8 x i32> @mgather_baseidx_zext_v8i16_v8i32(ptr %base, <8 x i16> %idxs, <
32913291
; RV64ZVE32F-NEXT: add a3, a0, a3
32923292
; RV64ZVE32F-NEXT: lw a3, 0(a3)
32933293
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
3294-
; RV64ZVE32F-NEXT: vmv.s.x v8, a3
3295-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
3294+
; RV64ZVE32F-NEXT: vmv.s.x v12, a3
3295+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
32963296
; RV64ZVE32F-NEXT: andi a3, a2, 32
32973297
; RV64ZVE32F-NEXT: bnez a3, .LBB40_8
32983298
; RV64ZVE32F-NEXT: j .LBB40_9
@@ -8157,9 +8157,9 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
81578157
; RV64ZVE32F-NEXT: add a2, a0, a2
81588158
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
81598159
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
8160-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8160+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
81618161
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
8162-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
8162+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
81638163
; RV64ZVE32F-NEXT: .LBB74_9: # %else14
81648164
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
81658165
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -8202,8 +8202,8 @@ define <8 x float> @mgather_baseidx_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <8 x i
82028202
; RV64ZVE32F-NEXT: add a2, a0, a2
82038203
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
82048204
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
8205-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8206-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
8205+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
8206+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
82078207
; RV64ZVE32F-NEXT: andi a2, a1, 32
82088208
; RV64ZVE32F-NEXT: bnez a2, .LBB74_8
82098209
; RV64ZVE32F-NEXT: j .LBB74_9
@@ -8307,9 +8307,9 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
83078307
; RV64ZVE32F-NEXT: add a2, a0, a2
83088308
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
83098309
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
8310-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8310+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
83118311
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
8312-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
8312+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
83138313
; RV64ZVE32F-NEXT: .LBB75_9: # %else14
83148314
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
83158315
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -8352,8 +8352,8 @@ define <8 x float> @mgather_baseidx_sext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
83528352
; RV64ZVE32F-NEXT: add a2, a0, a2
83538353
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
83548354
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
8355-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8356-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
8355+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
8356+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
83578357
; RV64ZVE32F-NEXT: andi a2, a1, 32
83588358
; RV64ZVE32F-NEXT: bnez a2, .LBB75_8
83598359
; RV64ZVE32F-NEXT: j .LBB75_9
@@ -8462,9 +8462,9 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
84628462
; RV64ZVE32F-NEXT: add a2, a0, a2
84638463
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
84648464
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
8465-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8465+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
84668466
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
8467-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
8467+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
84688468
; RV64ZVE32F-NEXT: .LBB76_9: # %else14
84698469
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
84708470
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -8510,8 +8510,8 @@ define <8 x float> @mgather_baseidx_zext_v8i8_v8f32(ptr %base, <8 x i8> %idxs, <
85108510
; RV64ZVE32F-NEXT: add a2, a0, a2
85118511
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
85128512
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
8513-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8514-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
8513+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
8514+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
85158515
; RV64ZVE32F-NEXT: andi a2, a1, 32
85168516
; RV64ZVE32F-NEXT: bnez a2, .LBB76_8
85178517
; RV64ZVE32F-NEXT: j .LBB76_9
@@ -8619,9 +8619,9 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
86198619
; RV64ZVE32F-NEXT: add a2, a0, a2
86208620
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
86218621
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
8622-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8622+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
86238623
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
8624-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
8624+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
86258625
; RV64ZVE32F-NEXT: .LBB77_9: # %else14
86268626
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
86278627
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -8664,8 +8664,8 @@ define <8 x float> @mgather_baseidx_v8i16_v8f32(ptr %base, <8 x i16> %idxs, <8 x
86648664
; RV64ZVE32F-NEXT: add a2, a0, a2
86658665
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
86668666
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
8667-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8668-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
8667+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
8668+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
86698669
; RV64ZVE32F-NEXT: andi a2, a1, 32
86708670
; RV64ZVE32F-NEXT: bnez a2, .LBB77_8
86718671
; RV64ZVE32F-NEXT: j .LBB77_9
@@ -8770,9 +8770,9 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
87708770
; RV64ZVE32F-NEXT: add a2, a0, a2
87718771
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
87728772
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
8773-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8773+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
87748774
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
8775-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
8775+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
87768776
; RV64ZVE32F-NEXT: .LBB78_9: # %else14
87778777
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
87788778
; RV64ZVE32F-NEXT: andi a2, a1, 64
@@ -8815,8 +8815,8 @@ define <8 x float> @mgather_baseidx_sext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
88158815
; RV64ZVE32F-NEXT: add a2, a0, a2
88168816
; RV64ZVE32F-NEXT: flw fa5, 0(a2)
88178817
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
8818-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8819-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
8818+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
8819+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
88208820
; RV64ZVE32F-NEXT: andi a2, a1, 32
88218821
; RV64ZVE32F-NEXT: bnez a2, .LBB78_8
88228822
; RV64ZVE32F-NEXT: j .LBB78_9
@@ -8926,9 +8926,9 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
89268926
; RV64ZVE32F-NEXT: add a3, a0, a3
89278927
; RV64ZVE32F-NEXT: flw fa5, 0(a3)
89288928
; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
8929-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8929+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
89308930
; RV64ZVE32F-NEXT: vsetivli zero, 6, e32, m2, tu, ma
8931-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 5
8931+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 5
89328932
; RV64ZVE32F-NEXT: .LBB79_9: # %else14
89338933
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
89348934
; RV64ZVE32F-NEXT: andi a3, a2, 64
@@ -8974,8 +8974,8 @@ define <8 x float> @mgather_baseidx_zext_v8i16_v8f32(ptr %base, <8 x i16> %idxs,
89748974
; RV64ZVE32F-NEXT: add a3, a0, a3
89758975
; RV64ZVE32F-NEXT: flw fa5, 0(a3)
89768976
; RV64ZVE32F-NEXT: vsetivli zero, 5, e32, m2, tu, ma
8977-
; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5
8978-
; RV64ZVE32F-NEXT: vslideup.vi v10, v8, 4
8977+
; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5
8978+
; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 4
89798979
; RV64ZVE32F-NEXT: andi a3, a2, 32
89808980
; RV64ZVE32F-NEXT: bnez a3, .LBB79_8
89818981
; RV64ZVE32F-NEXT: j .LBB79_9

‎llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -296,12 +296,12 @@ define <8 x i32> @v4i32_2(<4 x i32> %a, <4 x i32> %b) {
296296
; CHECK: # %bb.0:
297297
; CHECK-NEXT: vmv1r.v v12, v9
298298
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
299-
; CHECK-NEXT: vid.v v9
300-
; CHECK-NEXT: vrsub.vi v13, v9, 7
299+
; CHECK-NEXT: vid.v v13
300+
; CHECK-NEXT: vrsub.vi v14, v13, 7
301301
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
302-
; CHECK-NEXT: vrgatherei16.vv v10, v8, v13
302+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v14
303303
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
304-
; CHECK-NEXT: vrsub.vi v8, v9, 3
304+
; CHECK-NEXT: vrsub.vi v8, v13, 3
305305
; CHECK-NEXT: vmv.v.i v0, 15
306306
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
307307
; CHECK-NEXT: vrgatherei16.vv v10, v12, v8, v0.t
@@ -331,12 +331,12 @@ define <16 x i32> @v8i32_2(<8 x i32> %a, <8 x i32> %b) {
331331
; CHECK-NEXT: vmv2r.v v16, v10
332332
; CHECK-NEXT: vmv2r.v v12, v8
333333
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
334-
; CHECK-NEXT: vid.v v14
335-
; CHECK-NEXT: vrsub.vi v18, v14, 15
334+
; CHECK-NEXT: vid.v v18
335+
; CHECK-NEXT: vrsub.vi v20, v18, 15
336336
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
337-
; CHECK-NEXT: vrgatherei16.vv v8, v12, v18
337+
; CHECK-NEXT: vrgatherei16.vv v8, v12, v20
338338
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
339-
; CHECK-NEXT: vrsub.vi v12, v14, 7
339+
; CHECK-NEXT: vrsub.vi v12, v18, 7
340340
; CHECK-NEXT: li a0, 255
341341
; CHECK-NEXT: vmv.s.x v0, a0
342342
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -367,10 +367,10 @@ define <32 x i32> @v16i32_2(<16 x i32> %a, <16 x i32> %b) {
367367
; CHECK-NEXT: addi a0, a0, %lo(.LCPI23_0)
368368
; CHECK-NEXT: li a1, 32
369369
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
370-
; CHECK-NEXT: vle16.v v20, (a0)
370+
; CHECK-NEXT: vle16.v v28, (a0)
371371
; CHECK-NEXT: vmv4r.v v24, v12
372372
; CHECK-NEXT: vmv4r.v v16, v8
373-
; CHECK-NEXT: vrgatherei16.vv v8, v16, v20
373+
; CHECK-NEXT: vrgatherei16.vv v8, v16, v28
374374
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
375375
; CHECK-NEXT: vid.v v16
376376
; CHECK-NEXT: vrsub.vi v16, v16, 15
@@ -430,12 +430,12 @@ define <8 x i64> @v4i64_2(<4 x i64> %a, <4 x i64> %b) {
430430
; CHECK: # %bb.0:
431431
; CHECK-NEXT: vmv2r.v v16, v10
432432
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
433-
; CHECK-NEXT: vid.v v10
434-
; CHECK-NEXT: vrsub.vi v11, v10, 7
433+
; CHECK-NEXT: vid.v v18
434+
; CHECK-NEXT: vrsub.vi v19, v18, 7
435435
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
436-
; CHECK-NEXT: vrgatherei16.vv v12, v8, v11
436+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v19
437437
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
438-
; CHECK-NEXT: vrsub.vi v8, v10, 3
438+
; CHECK-NEXT: vrsub.vi v8, v18, 3
439439
; CHECK-NEXT: vmv.v.i v0, 15
440440
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
441441
; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
@@ -605,12 +605,12 @@ define <8 x float> @v4f32_2(<4 x float> %a, <4 x float> %b) {
605605
; CHECK: # %bb.0:
606606
; CHECK-NEXT: vmv1r.v v12, v9
607607
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
608-
; CHECK-NEXT: vid.v v9
609-
; CHECK-NEXT: vrsub.vi v13, v9, 7
608+
; CHECK-NEXT: vid.v v13
609+
; CHECK-NEXT: vrsub.vi v14, v13, 7
610610
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
611-
; CHECK-NEXT: vrgatherei16.vv v10, v8, v13
611+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v14
612612
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
613-
; CHECK-NEXT: vrsub.vi v8, v9, 3
613+
; CHECK-NEXT: vrsub.vi v8, v13, 3
614614
; CHECK-NEXT: vmv.v.i v0, 15
615615
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
616616
; CHECK-NEXT: vrgatherei16.vv v10, v12, v8, v0.t
@@ -640,12 +640,12 @@ define <16 x float> @v8f32_2(<8 x float> %a, <8 x float> %b) {
640640
; CHECK-NEXT: vmv2r.v v16, v10
641641
; CHECK-NEXT: vmv2r.v v12, v8
642642
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
643-
; CHECK-NEXT: vid.v v14
644-
; CHECK-NEXT: vrsub.vi v18, v14, 15
643+
; CHECK-NEXT: vid.v v18
644+
; CHECK-NEXT: vrsub.vi v20, v18, 15
645645
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
646-
; CHECK-NEXT: vrgatherei16.vv v8, v12, v18
646+
; CHECK-NEXT: vrgatherei16.vv v8, v12, v20
647647
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
648-
; CHECK-NEXT: vrsub.vi v12, v14, 7
648+
; CHECK-NEXT: vrsub.vi v12, v18, 7
649649
; CHECK-NEXT: li a0, 255
650650
; CHECK-NEXT: vmv.s.x v0, a0
651651
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
@@ -701,12 +701,12 @@ define <8 x double> @v4f64_2(<4 x double> %a, <4 x double> %b) {
701701
; CHECK: # %bb.0:
702702
; CHECK-NEXT: vmv2r.v v16, v10
703703
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
704-
; CHECK-NEXT: vid.v v10
705-
; CHECK-NEXT: vrsub.vi v11, v10, 7
704+
; CHECK-NEXT: vid.v v18
705+
; CHECK-NEXT: vrsub.vi v19, v18, 7
706706
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
707-
; CHECK-NEXT: vrgatherei16.vv v12, v8, v11
707+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v19
708708
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
709-
; CHECK-NEXT: vrsub.vi v8, v10, 3
709+
; CHECK-NEXT: vrsub.vi v8, v18, 3
710710
; CHECK-NEXT: vmv.v.i v0, 15
711711
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
712712
; CHECK-NEXT: vrgatherei16.vv v12, v16, v8, v0.t

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