pre-commit tests

Author: el-ev

llvm/test/CodeGen/RISCV/mul-expand.ll

@@ -0,0 +1,254 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+define i32 @muli32_0x555(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x555:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a1, 1365
+; RV32I-NEXT:    tail __mulsi3
+;
+; RV64I-LABEL: muli32_0x555:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    li a1, 1365
+; RV64I-NEXT:    call __muldi3
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+  %a1 = mul i32 %a, 1365
+  ret i32 %a1
+}
+
+define i64 @muli64_0x555(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x555:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    li a2, 1365
+; RV32I-NEXT:    li a3, 0
+; RV32I-NEXT:    call __muldi3
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: muli64_0x555:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 1365
+; RV64I-NEXT:    tail __muldi3
+  %a1 = mul i64 %a, 1365
+  ret i64 %a1
+}
+
+define i32 @muli32_0x33333333(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x33333333:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 209715
+; RV32I-NEXT:    addi a1, a1, 819
+; RV32I-NEXT:    tail __mulsi3
+;
+; RV64I-LABEL: muli32_0x33333333:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    lui a1, 209715
+; RV64I-NEXT:    addiw a1, a1, 819
+; RV64I-NEXT:    call __muldi3
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+    %a1 = mul i32 %a, 858993459
+    ret i32 %a1
+}
+
+define i64 @muli64_0x33333333(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x33333333:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    lui a2, 209715
+; RV32I-NEXT:    addi a2, a2, 819
+; RV32I-NEXT:    li a3, 0
+; RV32I-NEXT:    call __muldi3
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: muli64_0x33333333:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 209715
+; RV64I-NEXT:    addiw a1, a1, 819
+; RV64I-NEXT:    tail __muldi3
+    %a1 = mul i64 %a, 858993459
+    ret i64 %a1
+}
+
+define i32 @muli32_0xaaaaaaaa(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xaaaaaaaa:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 699051
+; RV32I-NEXT:    addi a1, a1, -1366
+; RV32I-NEXT:    tail __mulsi3
+;
+; RV64I-LABEL: muli32_0xaaaaaaaa:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    lui a1, 699051
+; RV64I-NEXT:    addiw a1, a1, -1366
+; RV64I-NEXT:    call __muldi3
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+  %a1 = mul i32 %a, -1431655766
+  ret i32 %a1
+}
+
+define i64 @muli64_0xaaaaaaaa(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xaaaaaaaa:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    lui a2, 699051
+; RV32I-NEXT:    addi a2, a2, -1366
+; RV32I-NEXT:    li a3, -1
+; RV32I-NEXT:    call __muldi3
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: muli64_0xaaaaaaaa:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 699051
+; RV64I-NEXT:    addiw a1, a1, -1366
+; RV64I-NEXT:    tail __muldi3
+  %a1 = mul i64 %a, -1431655766
+  ret i64 %a1
+}
+
+define i32 @muli32_0x0fffffff(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0x0fffffff:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a1, a0, 28
+; RV32I-NEXT:    sub a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: muli32_0x0fffffff:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a1, a0, 28
+; RV64I-NEXT:    subw a0, a1, a0
+; RV64I-NEXT:    ret
+  %a1 = mul i32 %a, 268435455
+  ret i32 %a1
+}
+
+define i64 @muli64_0x0fffffff(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0x0fffffff:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a2, a0, 28
+; RV32I-NEXT:    srli a3, a0, 4
+; RV32I-NEXT:    slli a4, a1, 28
+; RV32I-NEXT:    sltu a5, a2, a0
+; RV32I-NEXT:    or a3, a4, a3
+; RV32I-NEXT:    sub a1, a3, a1
+; RV32I-NEXT:    sub a1, a1, a5
+; RV32I-NEXT:    sub a0, a2, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: muli64_0x0fffffff:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a1, a0, 28
+; RV64I-NEXT:    sub a0, a1, a0
+; RV64I-NEXT:    ret
+  %a1 = mul i64 %a, 268435455
+  ret i64 %a1
+}
+
+define i32 @muli32_0xf0f0f0f0f0(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xf0f0f0f0f0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 986895
+; RV32I-NEXT:    addi a1, a1, 240
+; RV32I-NEXT:    tail __mulsi3
+;
+; RV64I-LABEL: muli32_0xf0f0f0f0f0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    lui a1, 986895
+; RV64I-NEXT:    addiw a1, a1, 240
+; RV64I-NEXT:    call __muldi3
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+  %a1 = mul i32 %a, -252645136
+  ret i32 %a1
+}
+
+define i64 @muli64_0xf0f0f0f0f0(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xf0f0f0f0f0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    lui a2, 986895
+; RV32I-NEXT:    addi a2, a2, 240
+; RV32I-NEXT:    li a3, -1
+; RV32I-NEXT:    call __muldi3
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: muli64_0xf0f0f0f0f0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 986895
+; RV64I-NEXT:    addiw a1, a1, 240
+; RV64I-NEXT:    tail __muldi3
+  %a1 = mul i64 %a, -252645136
+  ret i64 %a1
+}
+
+define i32 @muli32_0xf7f7f7f7(i32 %a) nounwind {
+; RV32I-LABEL: muli32_0xf7f7f7f7:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1015679
+; RV32I-NEXT:    addi a1, a1, 2039
+; RV32I-NEXT:    tail __mulsi3
+;
+; RV64I-LABEL: muli32_0xf7f7f7f7:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    lui a1, 1015679
+; RV64I-NEXT:    addiw a1, a1, 2039
+; RV64I-NEXT:    call __muldi3
+; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+  %a1 = mul i32 %a, -134744073
+  ret i32 %a1
+}
+
+define i64 @muli64_0xf7f7f7f7(i64 %a) nounwind {
+; RV32I-LABEL: muli64_0xf7f7f7f7:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    lui a2, 1015679
+; RV32I-NEXT:    addi a2, a2, 2039
+; RV32I-NEXT:    li a3, -1
+; RV32I-NEXT:    call __muldi3
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: muli64_0xf7f7f7f7:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1015679
+; RV64I-NEXT:    addiw a1, a1, 2039
+; RV64I-NEXT:    tail __muldi3
+  %a1 = mul i64 %a, -134744073
+  ret i64 %a1
+}