Skip to content

Commit 8ba334b

Browse files
gargaroffgargaroff
authored
[MIR] Allow overriding isSSA, noPhis, noVRegs in MIR input (#108546)
Allow setting the computed properties IsSSA, NoPHIs, NoVRegs for MIR functions in MIR input. The default value is still the computed value. If the property is set to false, the computed result is ignored. Conflicting values (e.g. setting IsSSA where the input MIR is clearly not SSA) lead to an error. Closes #37787
1 parent 3e3780e commit 8ba334b

11 files changed

+170
-18
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -730,6 +730,11 @@ struct MachineFunction {
730730
bool TracksRegLiveness = false;
731731
bool HasWinCFI = false;
732732

733+
// Computed properties that should be overridable
734+
std::optional<bool> NoPHIs;
735+
std::optional<bool> IsSSA;
736+
std::optional<bool> NoVRegs;
737+
733738
bool CallsEHReturn = false;
734739
bool CallsUnwindInit = false;
735740
bool HasEHCatchret = false;
@@ -770,6 +775,12 @@ template <> struct MappingTraits<MachineFunction> {
770775
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false);
771776
YamlIO.mapOptional("hasWinCFI", MF.HasWinCFI, false);
772777

778+
// PHIs must be not be capitalized, since it will clash with the MIR opcode
779+
// leading to false-positive FileCheck hits with CHECK-NOT
780+
YamlIO.mapOptional("noPhis", MF.NoPHIs, std::optional<bool>());
781+
YamlIO.mapOptional("isSSA", MF.IsSSA, std::optional<bool>());
782+
YamlIO.mapOptional("noVRegs", MF.NoVRegs, std::optional<bool>());
783+
773784
YamlIO.mapOptional("callsEHReturn", MF.CallsEHReturn, false);
774785
YamlIO.mapOptional("callsUnwindInit", MF.CallsUnwindInit, false);
775786
YamlIO.mapOptional("hasEHCatchret", MF.HasEHCatchret, false);

‎llvm/lib/CodeGen/MIRParser/MIRParser.cpp

Lines changed: 41 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,8 @@ class MIRParserImpl {
178178
SMDiagnostic diagFromBlockStringDiag(const SMDiagnostic &Error,
179179
SMRange SourceRange);
180180

181-
void computeFunctionProperties(MachineFunction &MF);
181+
bool computeFunctionProperties(MachineFunction &MF,
182+
const yaml::MachineFunction &YamlMF);
182183

183184
void setupDebugValueTracking(MachineFunction &MF,
184185
PerFunctionMIParsingState &PFS, const yaml::MachineFunction &YamlMF);
@@ -373,7 +374,8 @@ static bool isSSA(const MachineFunction &MF) {
373374
return true;
374375
}
375376

376-
void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
377+
bool MIRParserImpl::computeFunctionProperties(
378+
MachineFunction &MF, const yaml::MachineFunction &YamlMF) {
377379
MachineFunctionProperties &Properties = MF.getProperties();
378380

379381
bool HasPHI = false;
@@ -398,21 +400,48 @@ void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
398400
}
399401
}
400402
}
401-
if (!HasPHI)
402-
Properties.set(MachineFunctionProperties::Property::NoPHIs);
403+
404+
// Helper function to sanity-check and set properties that are computed, but
405+
// may be explicitly set from the input MIR
406+
auto ComputedPropertyHelper =
407+
[&Properties](std::optional<bool> ExplicitProp, bool ComputedProp,
408+
MachineFunctionProperties::Property P) -> bool {
409+
// Prefer explicitly given values over the computed properties
410+
if (ExplicitProp.value_or(ComputedProp))
411+
Properties.set(P);
412+
else
413+
Properties.reset(P);
414+
415+
// Check for conflict between the explicit values and the computed ones
416+
return ExplicitProp && *ExplicitProp && !ComputedProp;
417+
};
418+
419+
if (ComputedPropertyHelper(YamlMF.NoPHIs, !HasPHI,
420+
MachineFunctionProperties::Property::NoPHIs)) {
421+
return error(MF.getName() +
422+
" has explicit property NoPhi, but contains at least one PHI");
423+
}
424+
403425
MF.setHasInlineAsm(HasInlineAsm);
404426

405427
if (HasTiedOps && AllTiedOpsRewritten)
406428
Properties.set(MachineFunctionProperties::Property::TiedOpsRewritten);
407429

408-
if (isSSA(MF))
409-
Properties.set(MachineFunctionProperties::Property::IsSSA);
410-
else
411-
Properties.reset(MachineFunctionProperties::Property::IsSSA);
430+
if (ComputedPropertyHelper(YamlMF.IsSSA, isSSA(MF),
431+
MachineFunctionProperties::Property::IsSSA)) {
432+
return error(MF.getName() +
433+
" has explicit property IsSSA, but is not valid SSA");
434+
}
412435

413436
const MachineRegisterInfo &MRI = MF.getRegInfo();
414-
if (MRI.getNumVirtRegs() == 0)
415-
Properties.set(MachineFunctionProperties::Property::NoVRegs);
437+
if (ComputedPropertyHelper(YamlMF.NoVRegs, MRI.getNumVirtRegs() == 0,
438+
MachineFunctionProperties::Property::NoVRegs)) {
439+
return error(
440+
MF.getName() +
441+
" has explicit property NoVRegs, but contains virtual registers");
442+
}
443+
444+
return false;
416445
}
417446

418447
bool MIRParserImpl::initializeCallSiteInfo(
@@ -595,7 +624,8 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
595624
MachineRegisterInfo &MRI = MF.getRegInfo();
596625
MRI.freezeReservedRegs();
597626

598-
computeFunctionProperties(MF);
627+
if (computeFunctionProperties(MF, YamlMF))
628+
return false;
599629

600630
if (initializeCallSiteInfo(PFS, YamlMF))
601631
return false;

‎llvm/lib/CodeGen/MIRPrinter.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,13 @@ void MIRPrinter::print(const MachineFunction &MF) {
223223
YamlMF.TracksDebugUserValues = MF.getProperties().hasProperty(
224224
MachineFunctionProperties::Property::TracksDebugUserValues);
225225

226+
YamlMF.NoPHIs = MF.getProperties().hasProperty(
227+
MachineFunctionProperties::Property::NoPHIs);
228+
YamlMF.IsSSA = MF.getProperties().hasProperty(
229+
MachineFunctionProperties::Property::IsSSA);
230+
YamlMF.NoVRegs = MF.getProperties().hasProperty(
231+
MachineFunctionProperties::Property::NoVRegs);
232+
226233
convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
227234
MachineModuleSlotTracker MST(MMI, &MF);
228235
MST.incorporateFunction(MF.getFunction());

‎llvm/test/CodeGen/AArch64/mlicm-stack-write-check.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
---
44
name: test
55
tracksRegLiveness: true
6+
isSSA: false
67
registers:
78
- { id: 0, class: gpr64 }
89
stack:
@@ -30,11 +31,11 @@ body: |
3031
bb.2:
3132
liveins: $x0
3233
%0 = COPY $x0
33-
%0 = COPY $x0 ; Force isSSA = false.
3434
...
3535
---
3636
name: test2
3737
tracksRegLiveness: true
38+
isSSA: false
3839
registers:
3940
- { id: 0, class: gpr64 }
4041
stack:
@@ -62,5 +63,4 @@ body: |
6263
bb.2:
6364
liveins: $x0
6465
%0 = COPY $x0
65-
%0 = COPY $x0 ; Force isSSA = false.
6666
...

‎llvm/test/CodeGen/Hexagon/expand-condsets-impuse2.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,12 @@
66

77
name: f0
88
tracksRegLiveness: true
9+
isSSA: false
910
body: |
1011
bb.0:
1112
successors: %bb.1
1213
liveins: $r0, $r1
1314
%0:intregs = COPY $r0
14-
%0:intregs = COPY $r0 ; defeat IsSSA detection
1515
%1:intregs = COPY $r1
1616
%2:intregs = COPY $r0
1717
%3:intregs = M2_mpyi %2, %1

‎llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,12 @@
99

1010
name: fred
1111
tracksRegLiveness: true
12+
isSSA: false
1213
body: |
1314
bb.0:
1415
successors: %bb.1, %bb.2
1516
liveins: $r0
1617
17-
%0:intregs = A2_tfrsi 0 ;; Multiple defs to ensure IsSSA = false
1818
%0:intregs = L2_loadri_io $r0, 0
1919
%1:predregs = C2_cmpgti %0, 10
2020
%2:intregs = C2_mux %1, $r31, %0

‎llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020

2121
name: fred
2222
tracksRegLiveness: true
23+
isSSA: false
2324
registers:
2425
- { id: 0, class: intregs }
2526
- { id: 1, class: intregs }
@@ -35,7 +36,6 @@ body: |
3536
bb.0:
3637
liveins: $r0, $r1, $p0
3738
%0 = COPY $r0
38-
%0 = COPY $r0 ; Force isSSA = false.
3939
%1 = COPY $r1
4040
%2 = COPY $p0
4141
; Check that %3 was coalesced into %4.

‎llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties-conflict.mir

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
2+
3+
# Test that computed properties are not conflicting with explicitly set
4+
# properties
5+
6+
---
7+
# CHECK: error: {{.*}}: TestNoPhisOverrideConflict has explicit property NoPhi, but contains at least one PHI
8+
name: TestNoPhisOverrideConflict
9+
noPhis: true
10+
tracksRegLiveness: true
11+
body: |
12+
bb.0:
13+
%0:_(s32) = G_IMPLICIT_DEF
14+
15+
bb.1:
16+
%1:_(s32) = PHI %0, %bb.0, %1, %bb.1
17+
G_BR %bb.1
18+
...
19+
---
20+
# CHECK: error: {{.*}}: TestIsSSAOverrideConflict has explicit property IsSSA, but is not valid SSA
21+
name: TestIsSSAOverrideConflict
22+
isSSA: true
23+
body: |
24+
bb.0:
25+
%0:_(s32) = G_IMPLICIT_DEF
26+
%0:_(s32) = G_IMPLICIT_DEF
27+
...
28+
---
29+
# CHECK: error: {{.*}}: TestNoVRegsOverrideConflict has explicit property NoVRegs, but contains virtual registers
30+
name: TestNoVRegsOverrideConflict
31+
noVRegs: true
32+
body: |
33+
bb.0:
34+
%0:_(s32) = G_IMPLICIT_DEF
35+
...

‎llvm/test/CodeGen/MIR/Generic/machine-function-optionally-computed-properties.mir

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
# RUN: llc -run-pass none -o - %s | FileCheck %s
2+
3+
# Test that we can disable certain properties that are normally computed
4+
5+
---
6+
# CHECK-LABEL: name: TestNoPhis
7+
# CHECK: noPhis: true
8+
# CHECK: ...
9+
name: TestNoPhis
10+
...
11+
---
12+
# CHECK-LABEL: name: TestNoPhisOverride
13+
# CHECK: noPhis: false
14+
# CHECK: ...
15+
name: TestNoPhisOverride
16+
noPhis: false
17+
...
18+
---
19+
# CHECK-LABEL: name: TestNoPhisOverrideTrue
20+
# CHECK: noPhis: true
21+
# CHECK: ...
22+
name: TestNoPhisOverrideTrue
23+
noPhis: true
24+
...
25+
---
26+
# CHECK-LABEL: name: TestIsSSA
27+
# CHECK: isSSA: true
28+
# CHECK: ...
29+
name: TestIsSSA
30+
...
31+
---
32+
# CHECK-LABEL: name: TestIsSSAOverride
33+
# CHECK: isSSA: false
34+
# CHECK: ...
35+
name: TestIsSSAOverride
36+
isSSA: false
37+
...
38+
---
39+
# CHECK-LABEL: name: TestIsSSAOverrideTrue
40+
# CHECK: isSSA: true
41+
# CHECK: ...
42+
name: TestIsSSAOverrideTrue
43+
isSSA: true
44+
...
45+
---
46+
# CHECK-LABEL: name: TestNoVRegs
47+
# CHECK: noVRegs: true
48+
# CHECK: ...
49+
name: TestNoVRegs
50+
...
51+
---
52+
# CHECK-LABEL: name: TestNoVRegsOverride
53+
# CHECK: noVRegs: false
54+
# CHECK: ...
55+
name: TestNoVRegsOverride
56+
noVRegs: false
57+
...
58+
---
59+
# CHECK-LABEL: name: TestNoVRegsOverrideTrue
60+
# CHECK: noVRegs: true
61+
# CHECK: ...
62+
name: TestNoVRegsOverrideTrue
63+
noVRegs: true
64+
...

‎llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ name: bar
1414
# CHECK-LABEL: name: bar
1515
alignment: 16
1616
tracksRegLiveness: true
17+
noPhis: false
1718
body: |
1819
bb.0:
1920
%0:gr64 = IMPLICIT_DEF
@@ -29,8 +30,6 @@ body: |
2930
; CHECK-NOT: MOV64rm killed %0
3031
; CHECK-NEXT: MOV64rm killed %0
3132
32-
; FIXME: Dummy PHI to set the property NoPHIs to false. PR38439.
3333
bb.2:
34-
%1:gr64 = PHI undef %1, %bb.2, undef %1, %bb.2
3534
JMP_1 %bb.2
3635
...

‎llvm/test/tools/llvm-reduce/mir/preserve-func-info.mir

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,9 @@
1414
# RESULT-NEXT: failedISel: true
1515
# RESULT-NEXT: tracksRegLiveness: true
1616
# RESULT-NEXT: hasWinCFI: true
17+
# RESULT-NEXT: noPhis: false
18+
# RESULT-NEXT: isSSA: false
19+
# RESULT-NEXT: noVRegs: false
1720
# RESULT-NEXT: callsEHReturn: true
1821
# RESULT-NEXT: callsUnwindInit: true
1922
# RESULT-NEXT: hasEHCatchret: true
@@ -41,6 +44,9 @@ selected: true
4144
failedISel: true
4245
tracksRegLiveness: true
4346
hasWinCFI: true
47+
noPhis: false
48+
isSSA: false
49+
noVRegs: false
4450
failsVerification: true
4551
tracksDebugUserValues: true
4652
callsEHReturn: true

0 commit comments

Comments
 (0)