[AMDGPU] SIFixSGPRCopies should not process twice V2S copies created by PHI preprocessing

Author: alex-t

llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

@@ -127,6 +127,7 @@ class SIFixSGPRCopies {
   unsigned NextVGPRToSGPRCopyID = 0;
   MapVector<unsigned, V2SCopyInfo> V2SCopies;
   DenseMap<MachineInstr *, SetVector<unsigned>> SiblingPenalty;
+  DenseSet<MachineInstr *> PHISources;
 
 public:
   MachineRegisterInfo *MRI;
@@ -692,6 +693,7 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
                         .addReg(MO.getReg());
                 MO.setReg(NewDst);
                 analyzeVGPRToSGPRCopy(NewCopy);
+                PHISources.insert(NewCopy);
               }
             }
           }
@@ -798,6 +800,7 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
   RegSequences.clear();
   PHINodes.clear();
   S2VCopies.clear();
+  PHISources.clear();
 
   return true;
 }
@@ -923,6 +926,8 @@ bool SIFixSGPRCopies::lowerSpecialCase(MachineInstr &MI,
 }
 
 void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
+  if (PHISources.contains(MI))
+    return;
   Register DstReg = MI->getOperand(0).getReg();
   const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
 
@@ -966,9 +971,21 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
       }
     } else if (Inst->getNumExplicitDefs() != 0) {
       Register Reg = Inst->getOperand(0).getReg();
-      if (TRI->isSGPRReg(*MRI, Reg) && !TII->isVALU(*Inst))
-        for (auto &U : MRI->use_instructions(Reg))
-          Users.push_back(&U);
+      if (TRI->isSGPRReg(*MRI, Reg) && !TII->isVALU(*Inst)) {
+        if (Reg.isVirtual()) {
+          for (auto &U : MRI->use_instructions(Reg))
+            Users.push_back(&U);
+        } else {
+          auto I = Inst->getIterator();
+          auto E = Inst->getParent()->end();
+          while (++I != E) {
+            if (I->readsRegister(Reg, TRI))
+              Users.push_back(&*I);
+            if (I->modifiesRegister(Reg, TRI))
+              break;
+          }
+        }
+      }
     }
     for (auto *U : Users) {
       if (TII->isSALU(*U))

llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.ll

@@ -1114,19 +1114,23 @@ define amdgpu_kernel void @f64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[2:3], 0x0
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_add_f64 v[0:1], s[4:5], 1.0
-; GCN-NEXT:    v_and_b32_e32 v2, 0xffff0000, v1
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 2, v1
-; GCN-NEXT:    v_and_b32_e32 v3, 0xffff0000, v0
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 2, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GCN-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GCN-NEXT:    v_or_b32_e32 v1, v2, v1
-; GCN-NEXT:    v_or_b32_e32 v0, v3, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 0x20000, v1
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0x20000, v0
+; GCN-NEXT:    v_readfirstlane_b32 s2, v0
+; GCN-NEXT:    v_readfirstlane_b32 s4, v1
+; GCN-NEXT:    s_and_b32 s5, s4, 0xffff0000
+; GCN-NEXT:    s_add_i32 s4, s4, 2
+; GCN-NEXT:    s_and_b32 s6, s2, 0xffff0000
+; GCN-NEXT:    s_add_i32 s2, s2, 2
+; GCN-NEXT:    s_and_b32 s4, s4, 0xffff
+; GCN-NEXT:    s_and_b32 s2, s2, 0xffff
+; GCN-NEXT:    s_or_b32 s4, s5, s4
+; GCN-NEXT:    s_or_b32 s2, s6, s2
+; GCN-NEXT:    s_add_i32 s4, s4, 0x20000
+; GCN-NEXT:    s_add_i32 s5, s2, 0x20000
+; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    v_mov_b32_e32 v0, s5
+; GCN-NEXT:    v_mov_b32_e32 v1, s4
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
@@ -1139,14 +1143,20 @@ define amdgpu_kernel void @f64_to_v4i16(ptr addrspace(1) %out, ptr addrspace(1)
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_add_f64 v[0:1], s[2:3], 1.0
-; VI-NEXT:    v_and_b32_e32 v4, 0xffff0000, v0
-; VI-NEXT:    v_add_u32_e32 v0, vcc, 2, v0
-; VI-NEXT:    v_and_b32_e32 v5, 0xffff0000, v1
-; VI-NEXT:    v_add_u32_e32 v1, vcc, 2, v1
-; VI-NEXT:    v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-; VI-NEXT:    v_add_u32_e32 v1, vcc, 0x20000, v1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, 0x20000, v0
+; VI-NEXT:    v_readfirstlane_b32 s0, v1
+; VI-NEXT:    v_readfirstlane_b32 s1, v0
+; VI-NEXT:    s_and_b32 s2, s1, 0xffff0000
+; VI-NEXT:    s_add_i32 s1, s1, 2
+; VI-NEXT:    s_and_b32 s3, s0, 0xffff0000
+; VI-NEXT:    s_add_i32 s0, s0, 2
+; VI-NEXT:    s_and_b32 s0, s0, 0xffff
+; VI-NEXT:    s_and_b32 s1, s1, 0xffff
+; VI-NEXT:    s_or_b32 s0, s3, s0
+; VI-NEXT:    s_or_b32 s1, s2, s1
+; VI-NEXT:    s_add_i32 s0, s0, 0x20000
+; VI-NEXT:    s_add_i32 s1, s1, 0x20000
+; VI-NEXT:    v_mov_b32_e32 v0, s1
+; VI-NEXT:    v_mov_b32_e32 v1, s0
 ; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;

llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll

@@ -737,9 +737,7 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
 ; GFX908-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
 ; GFX908-NEXT:    s_mov_b64 s[4:5], -1
 ; GFX908-NEXT:    s_mov_b32 s6, 1
-; GFX908-NEXT:    v_readfirstlane_b32 s7, v2
-; GFX908-NEXT:    s_cmp_lg_u32 s7, s6
-; GFX908-NEXT:    s_cselect_b64 s[6:7], -1, 0
+; GFX908-NEXT:    v_cmp_ne_u32_e64 s[6:7], v2, s6
 ; GFX908-NEXT:    s_and_b64 vcc, exec, s[6:7]
 ; GFX908-NEXT:    ; implicit-def: $vgpr3_vgpr4
 ; GFX908-NEXT:    s_cbranch_vccnz .LBB5_2
@@ -808,9 +806,7 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
 ; GFX90A-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
 ; GFX90A-NEXT:    s_mov_b64 s[4:5], -1
 ; GFX90A-NEXT:    s_mov_b32 s6, 1
-; GFX90A-NEXT:    v_readfirstlane_b32 s7, v2
-; GFX90A-NEXT:    s_cmp_lg_u32 s7, s6
-; GFX90A-NEXT:    s_cselect_b64 s[6:7], -1, 0
+; GFX90A-NEXT:    v_cmp_ne_u32_e64 s[6:7], v2, s6
 ; GFX90A-NEXT:    s_and_b64 vcc, exec, s[6:7]
 ; GFX90A-NEXT:    ; implicit-def: $vgpr2_vgpr3
 ; GFX90A-NEXT:    s_cbranch_vccnz .LBB5_2
@@ -877,9 +873,7 @@ define double @optnone_atomicrmw_fadd_f64_expand(double %val) #1 {
 ; GFX942-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
 ; GFX942-NEXT:    s_mov_b64 s[0:1], -1
 ; GFX942-NEXT:    s_mov_b32 s2, 1
-; GFX942-NEXT:    v_readfirstlane_b32 s3, v2
-; GFX942-NEXT:    s_cmp_lg_u32 s3, s2
-; GFX942-NEXT:    s_cselect_b64 s[2:3], -1, 0
+; GFX942-NEXT:    v_cmp_ne_u32_e64 s[2:3], v2, s2
 ; GFX942-NEXT:    s_and_b64 vcc, exec, s[2:3]
 ; GFX942-NEXT:    ; implicit-def: $vgpr2_vgpr3
 ; GFX942-NEXT:    s_cbranch_vccnz .LBB5_2

llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-phi-regression-issue130646-issue130119.ll

@@ -0,0 +1,166 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
+
+; SGPR phi ends up with VGPR inputs. Make sure we do not try to
+; process a copy which has already been erased (which was already
+; inserted by the pass).
+
+define double @issue130646(i64 %arg) {
+; CHECK-LABEL: issue130646:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    s_mov_b64 s[4:5], 0
+; CHECK-NEXT:    s_branch .LBB0_2
+; CHECK-NEXT:  .LBB0_1: ; %for.body.5
+; CHECK-NEXT:    ; in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    s_lshr_b64 s[6:7], s[4:5], 1
+; CHECK-NEXT:    v_or_b32_e32 v3, s7, v3
+; CHECK-NEXT:    v_or_b32_e32 v2, s6, v2
+; CHECK-NEXT:    s_lshr_b64 s[6:7], s[4:5], 5
+; CHECK-NEXT:    s_or_b32 s6, s6, 1
+; CHECK-NEXT:    v_or3_b32 v3, v3, v1, s7
+; CHECK-NEXT:    v_or3_b32 v2, v2, v0, s6
+; CHECK-NEXT:    s_lshr_b64 s[4:5], s[4:5], 8
+; CHECK-NEXT:    s_cbranch_execz .LBB0_4
+; CHECK-NEXT:  .LBB0_2: ; %for.body
+; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    s_cmp_eq_u64 s[4:5], 0
+; CHECK-NEXT:    v_readfirstlane_b32 s8, v0
+; CHECK-NEXT:    v_readfirstlane_b32 s9, v1
+; CHECK-NEXT:    s_cbranch_scc0 .LBB0_1
+; CHECK-NEXT:  ; %bb.3:
+; CHECK-NEXT:    ; implicit-def: $vgpr2_vgpr3
+; CHECK-NEXT:    s_mov_b64 s[4:5], s[8:9]
+; CHECK-NEXT:  .LBB0_4: ; %for.cond.cleanup
+; CHECK-NEXT:    v_mov_b32_e32 v0, 0
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  br label %for.body
+
+for.cond.cleanup:                                 ; preds = %for.body
+  %cmp3.not.i.i.i = icmp eq i64 %r.0108, 0
+  br i1 %cmp3.not.i.i.i, label %cleanup, label %if.end26.i.i
+
+if.end26.i.i:                                     ; preds = %for.cond.cleanup
+  br label %cleanup
+
+for.body:                                         ; preds = %for.body.5, %entry
+  %current_bit.01093 = phi i64 [ 0, %entry ], [ %shr.3.7, %for.body.5 ]
+  %r.0108 = phi i64 [ 0, %entry ], [ %shl28.3.7, %for.body.5 ]
+  %shr.3 = lshr i64 %current_bit.01093, 1
+  %i = or i64 %r.0108, %shr.3
+  %i3 = or i64 %i, %arg
+  %tobool27.not.3.4 = icmp ult i64 %current_bit.01093, 1
+  br i1 %tobool27.not.3.4, label %for.cond.cleanup, label %for.body.5
+
+for.body.5:                                       ; preds = %for.body
+  %shr.3.4 = lshr i64 %current_bit.01093, 5
+  %i6 = or i64 %shr.3.4, 1
+  %shl28.3.7 = or i64 %i6, %i3
+  %shr.3.7 = lshr i64 %current_bit.01093, 8
+  br label %for.body
+
+cleanup:                                          ; preds = %if.end26.i.i, %for.cond.cleanup
+  ret double 0.000000e+00
+}
+
+define amdgpu_cs void @issue130119(i1 %arg) {
+; CHECK-LABEL: issue130119:
+; CHECK:       ; %bb.0: ; %bb
+; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[0:1], 1, v0
+; CHECK-NEXT:    s_mov_b32 s16, 0
+; CHECK-NEXT:    s_mov_b64 s[4:5], 0
+; CHECK-NEXT:    s_branch .LBB1_2
+; CHECK-NEXT:  .LBB1_1: ; %Flow2
+; CHECK-NEXT:    ; in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT:    s_or_b64 exec, exec, s[6:7]
+; CHECK-NEXT:    s_and_b64 s[2:3], exec, s[2:3]
+; CHECK-NEXT:    s_or_b64 s[4:5], s[2:3], s[4:5]
+; CHECK-NEXT:    s_andn2_b64 exec, exec, s[4:5]
+; CHECK-NEXT:    s_cbranch_execz .LBB1_10
+; CHECK-NEXT:  .LBB1_2: ; %bb1
+; CHECK-NEXT:    ; =>This Loop Header: Depth=1
+; CHECK-NEXT:    ; Child Loop BB1_4 Depth 2
+; CHECK-NEXT:    s_and_b32 s2, s16, 1
+; CHECK-NEXT:    s_cmp_eq_u32 s2, 0
+; CHECK-NEXT:    s_cselect_b64 s[6:7], -1, 0
+; CHECK-NEXT:    s_cmp_eq_u32 s2, 1
+; CHECK-NEXT:    s_cselect_b64 s[2:3], -1, 0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[2:3]
+; CHECK-NEXT:    v_cmp_ne_u32_e64 s[2:3], 1, v0
+; CHECK-NEXT:    s_mov_b64 s[10:11], 0
+; CHECK-NEXT:    ; implicit-def: $sgpr8_sgpr9
+; CHECK-NEXT:    s_branch .LBB1_4
+; CHECK-NEXT:  .LBB1_3: ; %Flow1
+; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT:    s_xor_b64 s[14:15], s[14:15], -1
+; CHECK-NEXT:    s_and_b64 s[12:13], exec, s[12:13]
+; CHECK-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
+; CHECK-NEXT:    s_andn2_b64 s[8:9], s[8:9], exec
+; CHECK-NEXT:    s_and_b64 s[12:13], s[14:15], exec
+; CHECK-NEXT:    s_or_b64 s[8:9], s[8:9], s[12:13]
+; CHECK-NEXT:    s_andn2_b64 exec, exec, s[10:11]
+; CHECK-NEXT:    s_cbranch_execz .LBB1_8
+; CHECK-NEXT:  .LBB1_4: ; %bb3
+; CHECK-NEXT:    ; Parent Loop BB1_2 Depth=1
+; CHECK-NEXT:    ; => This Inner Loop Header: Depth=2
+; CHECK-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CHECK-NEXT:    s_mov_b64 s[14:15], s[6:7]
+; CHECK-NEXT:    s_cbranch_vccnz .LBB1_6
+; CHECK-NEXT:  ; %bb.5: ; %bb7
+; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT:    s_mov_b64 s[14:15], -1
+; CHECK-NEXT:  .LBB1_6: ; %Flow
+; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT:    s_mov_b64 s[12:13], -1
+; CHECK-NEXT:    s_andn2_b64 vcc, exec, s[14:15]
+; CHECK-NEXT:    s_mov_b64 s[14:15], -1
+; CHECK-NEXT:    s_cbranch_vccnz .LBB1_3
+; CHECK-NEXT:  ; %bb.7: ; %bb8
+; CHECK-NEXT:    ; in Loop: Header=BB1_4 Depth=2
+; CHECK-NEXT:    s_mov_b64 s[14:15], 0
+; CHECK-NEXT:    s_orn2_b64 s[12:13], s[0:1], exec
+; CHECK-NEXT:    s_branch .LBB1_3
+; CHECK-NEXT:  .LBB1_8: ; %loop.exit.guard
+; CHECK-NEXT:    ; in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT:    s_or_b64 exec, exec, s[10:11]
+; CHECK-NEXT:    s_mov_b64 s[2:3], -1
+; CHECK-NEXT:    s_and_saveexec_b64 s[6:7], s[8:9]
+; CHECK-NEXT:    s_xor_b64 s[6:7], exec, s[6:7]
+; CHECK-NEXT:    s_cbranch_execz .LBB1_1
+; CHECK-NEXT:  ; %bb.9: ; %bb10
+; CHECK-NEXT:    ; in Loop: Header=BB1_2 Depth=1
+; CHECK-NEXT:    s_or_b32 s16, s16, 1
+; CHECK-NEXT:    s_xor_b64 s[2:3], exec, -1
+; CHECK-NEXT:    s_branch .LBB1_1
+; CHECK-NEXT:  .LBB1_10: ; %DummyReturnBlock
+; CHECK-NEXT:    s_endpgm
+bb:
+  br label %bb1
+
+bb1:                                              ; preds = %bb10, %bb
+  %i = phi i32 [ 0, %bb ], [ %i11, %bb10 ]
+  %i2 = phi i32 [ 0, %bb ], [ %i4, %bb10 ]
+  br label %bb3
+
+bb3:                                              ; preds = %bb8, %bb1
+  %i4 = phi i32 [ %i2, %bb1 ], [ %i9, %bb8 ]
+  %i5 = and i32 %i, 1
+  %i6 = icmp eq i32 %i5, 0
+  br i1 %i6, label %bb8, label %bb7
+
+bb7:                                              ; preds = %bb3
+  br label %bb8
+
+bb8:                                              ; preds = %bb7, %bb3
+  %i9 = phi i32 [ %i2, %bb3 ], [ 0, %bb7 ]
+  br i1 %arg, label %bb10, label %bb3
+
+bb10:                                             ; preds = %bb8
+  %i11 = or i32 %i, 1
+  br label %bb1
+}