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[ARM64EC] Fix arm_neon.h on ARM64EC. (#88572)
Since 97fe519, in ARM64EC mode, we don't define `__aarch64__`. Fix various preprocessor guards to account for this.
1 parent ce5381e commit 8c9f45e

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+34
-34
lines changed

3 files changed

+34
-34
lines changed

‎clang/include/clang/Basic/arm_fp16.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
include "arm_neon_incl.td"
1515

1616
// ARMv8.2-A FP16 intrinsics.
17-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "fullfp16" in {
17+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "fullfp16" in {
1818

1919
// Negate
2020
def VNEGSH : SInst<"vneg", "11", "Sh">;

‎clang/include/clang/Basic/arm_neon.td

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -605,11 +605,11 @@ def VQDMULL_LANE : SOpInst<"vqdmull_lane", "(>Q)..I", "si", OP_QDMULL_LN>;
605605
def VQDMULH_N : SOpInst<"vqdmulh_n", "..1", "siQsQi", OP_QDMULH_N>;
606606
def VQRDMULH_N : SOpInst<"vqrdmulh_n", "..1", "siQsQi", OP_QRDMULH_N>;
607607

608-
let ArchGuard = "!defined(__aarch64__)" in {
608+
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)" in {
609609
def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>;
610610
def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>;
611611
}
612-
let ArchGuard = "defined(__aarch64__)" in {
612+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
613613
def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi">;
614614
def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi">;
615615
}
@@ -686,7 +686,7 @@ multiclass REINTERPRET_CROSS_TYPES<string TypesA, string TypesB> {
686686

687687
// E.3.31 Vector reinterpret cast operations
688688
def VREINTERPRET : REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs"> {
689-
let ArchGuard = "!defined(__aarch64__)";
689+
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)";
690690
let BigEndianSafe = 1;
691691
}
692692

@@ -714,7 +714,7 @@ def VADDP : WInst<"vadd", "...", "PcPsPlQPcQPsQPl">;
714714
////////////////////////////////////////////////////////////////////////////////
715715
// AArch64 Intrinsics
716716

717-
let ArchGuard = "defined(__aarch64__)" in {
717+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
718718

719719
////////////////////////////////////////////////////////////////////////////////
720720
// Load/Store
@@ -1091,14 +1091,14 @@ let isLaneQ = 1 in {
10911091
def VQDMULH_LANEQ : SInst<"vqdmulh_laneq", "..QI", "siQsQi">;
10921092
def VQRDMULH_LANEQ : SInst<"vqrdmulh_laneq", "..QI", "siQsQi">;
10931093
}
1094-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a" in {
1094+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a" in {
10951095
def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", OP_QRDMLAH_LN> {
10961096
let isLaneQ = 1;
10971097
}
10981098
def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "...QI", "siQsQi", OP_QRDMLSH_LN> {
10991099
let isLaneQ = 1;
11001100
}
1101-
} // ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a"
1101+
} // ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a"
11021102

11031103
// Note: d type implemented by SCALAR_VMULX_LANE
11041104
def VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "fQfQd", OP_MULX_LN>;
@@ -1143,7 +1143,7 @@ def SHA256H2 : SInst<"vsha256h2", "....", "QUi">;
11431143
def SHA256SU1 : SInst<"vsha256su1", "....", "QUi">;
11441144
}
11451145

1146-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "sha3" in {
1146+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sha3" in {
11471147
def BCAX : SInst<"vbcax", "....", "QUcQUsQUiQUlQcQsQiQl">;
11481148
def EOR3 : SInst<"veor3", "....", "QUcQUsQUiQUlQcQsQiQl">;
11491149
def RAX1 : SInst<"vrax1", "...", "QUl">;
@@ -1153,14 +1153,14 @@ def XAR : SInst<"vxar", "...I", "QUl">;
11531153
}
11541154
}
11551155

1156-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "sha3" in {
1156+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sha3" in {
11571157
def SHA512SU0 : SInst<"vsha512su0", "...", "QUl">;
11581158
def SHA512su1 : SInst<"vsha512su1", "....", "QUl">;
11591159
def SHA512H : SInst<"vsha512h", "....", "QUl">;
11601160
def SHA512H2 : SInst<"vsha512h2", "....", "QUl">;
11611161
}
11621162

1163-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "sm4" in {
1163+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sm4" in {
11641164
def SM3SS1 : SInst<"vsm3ss1", "....", "QUi">;
11651165
def SM3TT1A : SInst<"vsm3tt1a", "....I", "QUi">;
11661166
def SM3TT1B : SInst<"vsm3tt1b", "....I", "QUi">;
@@ -1170,7 +1170,7 @@ def SM3PARTW1 : SInst<"vsm3partw1", "....", "QUi">;
11701170
def SM3PARTW2 : SInst<"vsm3partw2", "....", "QUi">;
11711171
}
11721172

1173-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "sm4" in {
1173+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "sm4" in {
11741174
def SM4E : SInst<"vsm4e", "...", "QUi">;
11751175
def SM4EKEY : SInst<"vsm4ekey", "...", "QUi">;
11761176
}
@@ -1193,7 +1193,7 @@ def FCVTAS_S32 : SInst<"vcvta_s32", "S.", "fQf">;
11931193
def FCVTAU_S32 : SInst<"vcvta_u32", "U.", "fQf">;
11941194
}
11951195

1196-
let ArchGuard = "defined(__aarch64__)" in {
1196+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
11971197
def FCVTNS_S64 : SInst<"vcvtn_s64", "S.", "dQd">;
11981198
def FCVTNU_S64 : SInst<"vcvtn_u64", "U.", "dQd">;
11991199
def FCVTPS_S64 : SInst<"vcvtp_s64", "S.", "dQd">;
@@ -1217,7 +1217,7 @@ def FRINTZ_S32 : SInst<"vrnd", "..", "fQf">;
12171217
def FRINTI_S32 : SInst<"vrndi", "..", "fQf">;
12181218
}
12191219

1220-
let ArchGuard = "defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
1220+
let ArchGuard = "(defined(__aarch64__) || defined(__arm64ec__)) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
12211221
def FRINTN_S64 : SInst<"vrndn", "..", "dQd">;
12221222
def FRINTA_S64 : SInst<"vrnda", "..", "dQd">;
12231223
def FRINTP_S64 : SInst<"vrndp", "..", "dQd">;
@@ -1227,7 +1227,7 @@ def FRINTZ_S64 : SInst<"vrnd", "..", "dQd">;
12271227
def FRINTI_S64 : SInst<"vrndi", "..", "dQd">;
12281228
}
12291229

1230-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.5a" in {
1230+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.5a" in {
12311231
def FRINT32X_S32 : SInst<"vrnd32x", "..", "fQf">;
12321232
def FRINT32Z_S32 : SInst<"vrnd32z", "..", "fQf">;
12331233
def FRINT64X_S32 : SInst<"vrnd64x", "..", "fQf">;
@@ -1247,7 +1247,7 @@ def FMAXNM_S32 : SInst<"vmaxnm", "...", "fQf">;
12471247
def FMINNM_S32 : SInst<"vminnm", "...", "fQf">;
12481248
}
12491249

1250-
let ArchGuard = "defined(__aarch64__) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
1250+
let ArchGuard = "(defined(__aarch64__) || defined(__arm64ec__)) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in {
12511251
def FMAXNM_S64 : SInst<"vmaxnm", "...", "dQd">;
12521252
def FMINNM_S64 : SInst<"vminnm", "...", "dQd">;
12531253
}
@@ -1289,7 +1289,7 @@ def VQTBX4_A64 : WInst<"vqtbx4", "..(4Q)U", "UccPcQUcQcQPc">;
12891289
// itself during generation so, unlike all other intrinsics, this one should
12901290
// include *all* types, not just additional ones.
12911291
def VVREINTERPRET : REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk"> {
1292-
let ArchGuard = "defined(__aarch64__)";
1292+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)";
12931293
let BigEndianSafe = 1;
12941294
}
12951295

@@ -1401,15 +1401,15 @@ def SCALAR_SQDMULH : SInst<"vqdmulh", "111", "SsSi">;
14011401
// Scalar Integer Saturating Rounding Doubling Multiply Half High
14021402
def SCALAR_SQRDMULH : SInst<"vqrdmulh", "111", "SsSi">;
14031403

1404-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a" in {
1404+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a" in {
14051405
////////////////////////////////////////////////////////////////////////////////
14061406
// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
14071407
def SCALAR_SQRDMLAH : SInst<"vqrdmlah", "1111", "SsSi">;
14081408

14091409
////////////////////////////////////////////////////////////////////////////////
14101410
// Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
14111411
def SCALAR_SQRDMLSH : SInst<"vqrdmlsh", "1111", "SsSi">;
1412-
} // ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.1a"
1412+
} // ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.1a"
14131413

14141414
////////////////////////////////////////////////////////////////////////////////
14151415
// Scalar Floating-point Multiply Extended
@@ -1651,7 +1651,7 @@ def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "1QI", "ScSsSiSlSfSdSUcSUsSUiSUlSPcS
16511651
let isLaneQ = 1;
16521652
}
16531653

1654-
} // ArchGuard = "defined(__aarch64__)"
1654+
} // ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)"
16551655

16561656
// ARMv8.2-A FP16 vector intrinsics for A32/A64.
16571657
let TargetGuard = "fullfp16" in {
@@ -1775,7 +1775,7 @@ def VEXTH : WInst<"vext", "...I", "hQh">;
17751775
def VREV64H : WOpInst<"vrev64", "..", "hQh", OP_REV64>;
17761776

17771777
// ARMv8.2-A FP16 vector intrinsics for A64 only.
1778-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "fullfp16" in {
1778+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "fullfp16" in {
17791779

17801780
// Vector rounding
17811781
def FRINTIH : SInst<"vrndi", "..", "hQh">;
@@ -1856,7 +1856,7 @@ let ArchGuard = "defined(__aarch64__)", TargetGuard = "fullfp16" in {
18561856
def FMINNMVH : SInst<"vminnmv", "1.", "hQh">;
18571857
}
18581858

1859-
let ArchGuard = "defined(__aarch64__)" in {
1859+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
18601860
// Permutation
18611861
def VTRN1H : SOpInst<"vtrn1", "...", "hQh", OP_TRN1>;
18621862
def VZIP1H : SOpInst<"vzip1", "...", "hQh", OP_ZIP1>;
@@ -1876,15 +1876,15 @@ let TargetGuard = "dotprod" in {
18761876
def DOT : SInst<"vdot", "..(<<)(<<)", "iQiUiQUi">;
18771877
def DOT_LANE : SOpInst<"vdot_lane", "..(<<)(<<q)I", "iUiQiQUi", OP_DOT_LN>;
18781878
}
1879-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "dotprod" in {
1879+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "dotprod" in {
18801880
// Variants indexing into a 128-bit vector are A64 only.
18811881
def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<<Q)I", "iUiQiQUi", OP_DOT_LNQ> {
18821882
let isLaneQ = 1;
18831883
}
18841884
}
18851885

18861886
// v8.2-A FP16 fused multiply-add long instructions.
1887-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "fp16fml" in {
1887+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "fp16fml" in {
18881888
def VFMLAL_LOW : SInst<"vfmlal_low", ">>..", "hQh">;
18891889
def VFMLSL_LOW : SInst<"vfmlsl_low", ">>..", "hQh">;
18901890
def VFMLAL_HIGH : SInst<"vfmlal_high", ">>..", "hQh">;
@@ -1918,7 +1918,7 @@ let TargetGuard = "i8mm" in {
19181918
def VUSDOT_LANE : SOpInst<"vusdot_lane", "..(<<U)(<<q)I", "iQi", OP_USDOT_LN>;
19191919
def VSUDOT_LANE : SOpInst<"vsudot_lane", "..(<<)(<<qU)I", "iQi", OP_SUDOT_LN>;
19201920

1921-
let ArchGuard = "defined(__aarch64__)" in {
1921+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
19221922
let isLaneQ = 1 in {
19231923
def VUSDOT_LANEQ : SOpInst<"vusdot_laneq", "..(<<U)(<<Q)I", "iQi", OP_USDOT_LNQ>;
19241924
def VSUDOT_LANEQ : SOpInst<"vsudot_laneq", "..(<<)(<<QU)I", "iQi", OP_SUDOT_LNQ>;
@@ -1986,7 +1986,7 @@ let TargetGuard = "v8.3a" in {
19861986

19871987
defm VCMLA_F32 : VCMLA_ROTS<"f", "uint64x1_t", "uint64x2_t">;
19881988
}
1989-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "v8.3a" in {
1989+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "v8.3a" in {
19901990
def VCADDQ_ROT90_FP64 : SInst<"vcaddq_rot90", "QQQ", "d">;
19911991
def VCADDQ_ROT270_FP64 : SInst<"vcaddq_rot270", "QQQ", "d">;
19921992

@@ -2058,14 +2058,14 @@ let TargetGuard = "bf16" in {
20582058
def SCALAR_CVT_F32_BF16 : SOpInst<"vcvtah_f32", "(1F>)(1!)", "b", OP_CVT_F32_BF16>;
20592059
}
20602060

2061-
let ArchGuard = "!defined(__aarch64__)", TargetGuard = "bf16" in {
2061+
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)", TargetGuard = "bf16" in {
20622062
def VCVT_BF16_F32_A32_INTERNAL : WInst<"__a32_vcvt_bf16", "BQ", "f">;
20632063
def VCVT_BF16_F32_A32 : SOpInst<"vcvt_bf16", "BQ", "f", OP_VCVT_BF16_F32_A32>;
20642064
def VCVT_LOW_BF16_F32_A32 : SOpInst<"vcvt_low_bf16", "BQ", "Qf", OP_VCVT_BF16_F32_LO_A32>;
20652065
def VCVT_HIGH_BF16_F32_A32 : SOpInst<"vcvt_high_bf16", "BBQ", "Qf", OP_VCVT_BF16_F32_HI_A32>;
20662066
}
20672067

2068-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "bf16" in {
2068+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "bf16" in {
20692069
def VCVT_LOW_BF16_F32_A64_INTERNAL : WInst<"__a64_vcvtq_low_bf16", "BQ", "Hf">;
20702070
def VCVT_LOW_BF16_F32_A64 : SOpInst<"vcvt_low_bf16", "BQ", "Qf", OP_VCVT_BF16_F32_LO_A64>;
20712071
def VCVT_HIGH_BF16_F32_A64 : SInst<"vcvt_high_bf16", "BBQ", "Qf">;
@@ -2077,22 +2077,22 @@ let ArchGuard = "defined(__aarch64__)", TargetGuard = "bf16" in {
20772077
def COPYQ_LANEQ_BF16 : IOpInst<"vcopy_laneq", "..I.I", "Qb", OP_COPY_LN>;
20782078
}
20792079

2080-
let ArchGuard = "!defined(__aarch64__)", TargetGuard = "bf16" in {
2080+
let ArchGuard = "!defined(__aarch64__) && !defined(__arm64ec__)", TargetGuard = "bf16" in {
20812081
let BigEndianSafe = 1 in {
20822082
defm VREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
20832083
"csilUcUsUiUlhfPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQPcQPsQPl", "bQb">;
20842084
}
20852085
}
20862086

2087-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "bf16" in {
2087+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "bf16" in {
20882088
let BigEndianSafe = 1 in {
20892089
defm VVREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
20902090
"csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", "bQb">;
20912091
}
20922092
}
20932093

20942094
// v8.9a/v9.4a LRCPC3 intrinsics
2095-
let ArchGuard = "defined(__aarch64__)", TargetGuard = "rcpc3" in {
2095+
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "rcpc3" in {
20962096
def VLDAP1_LANE : WInst<"vldap1_lane", ".(c*!).I", "QUlQlUlldQdPlQPl">;
20972097
def VSTL1_LANE : WInst<"vstl1_lane", "v*(.!)I", "QUlQlUlldQdPlQPl">;
20982098
}

‎clang/utils/TableGen/NeonEmitter.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2266,7 +2266,7 @@ static void emitNeonTypeDefs(const std::string& types, raw_ostream &OS) {
22662266
InIfdef = false;
22672267
}
22682268
if (!InIfdef && IsA64) {
2269-
OS << "#ifdef __aarch64__\n";
2269+
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
22702270
InIfdef = true;
22712271
}
22722272

@@ -2299,7 +2299,7 @@ static void emitNeonTypeDefs(const std::string& types, raw_ostream &OS) {
22992299
InIfdef = false;
23002300
}
23012301
if (!InIfdef && IsA64) {
2302-
OS << "#ifdef __aarch64__\n";
2302+
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
23032303
InIfdef = true;
23042304
}
23052305

@@ -2381,7 +2381,7 @@ void NeonEmitter::run(raw_ostream &OS) {
23812381
OS << "#include <arm_vector_types.h>\n";
23822382

23832383
// For now, signedness of polynomial types depends on target
2384-
OS << "#ifdef __aarch64__\n";
2384+
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
23852385
OS << "typedef uint8_t poly8_t;\n";
23862386
OS << "typedef uint16_t poly16_t;\n";
23872387
OS << "typedef uint64_t poly64_t;\n";
@@ -2582,7 +2582,7 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
25822582
OS << "typedef float float32_t;\n";
25832583
OS << "typedef __fp16 float16_t;\n";
25842584

2585-
OS << "#ifdef __aarch64__\n";
2585+
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
25862586
OS << "typedef double float64_t;\n";
25872587
OS << "#endif\n\n";
25882588

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