@@ -68,7 +68,7 @@ class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
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}
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// op vd, vs2, imm
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- class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5 >
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+ class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
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: VALUVINoVm<funct6, opcodestr, optype> {
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let Inst{6-0} = OPC_OP_P.Value;
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let Inst{14-12} = OPMVV.Value;
@@ -85,14 +85,6 @@ multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
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def NAME # _VV : PALUVs2NoVm<funct6_vv, vs1, opv, opcodestr # ".vv">;
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def NAME # _VS : PALUVs2NoVm<funct6_vs, vs1, opv, opcodestr # ".vs">;
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}
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-
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- // vaeskf1.vi and vaeskf2.vi uses different opcode and format, we need
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- // to customize one for them.
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- class VAESKF_MV_I<bits<6> funct6, string opcodestr, Operand optype>
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- : VALUVINoVm<funct6, opcodestr, optype> {
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- let Inst{6-0} = OPC_OP_P.Value;
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- let Inst{14-12} = OPMVV.Value;
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- }
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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//===----------------------------------------------------------------------===//
@@ -137,8 +129,8 @@ let Predicates = [HasStdExtZvkned], RVVConstraint = NoConstraint in {
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defm VAESDM : VAES_MV_V_S<0b101000, 0b101001, 0b00000, OPMVV, "vaesdm">;
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defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
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defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
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- def VAESKF1_VI : VAESKF_MV_I <0b100010, "vaeskf1.vi", uimm5>;
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- def VAESKF2_VI : VAESKF_MV_I <0b101010, "vaeskf2.vi", uimm5>;
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+ def VAESKF1_VI : PALUVINoVm <0b100010, "vaeskf1.vi", uimm5>;
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+ def VAESKF2_VI : PALUVINoVm <0b101010, "vaeskf2.vi", uimm5>;
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def VAESZ_VS : PALUVs2NoVm<0b101001, 0b00111, OPMVV, "vaesz.vs">;
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} // Predicates = [HasStdExtZvkned]
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