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lines changed Original file line number Diff line number Diff line change @@ -2102,7 +2102,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
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SubVecContainerVT = TLI.getContainerForFixedLengthVector (SubVecVT);
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#ifndef NDEBUG
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TypeSize VecRegSize = TypeSize::getScalable (RISCV::RVVBitsPerBlock);
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- bool ExactlyVecRegSized =
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+ [[maybe_unused]] bool ExactlyVecRegSized =
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Subtarget->expandVScale (SubVecVT.getSizeInBits ())
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.isKnownMultipleOf (Subtarget->expandVScale (VecRegSize));
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assert (isPowerOf2_64 (Subtarget->expandVScale (SubVecVT.getSizeInBits ())
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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- ; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK, VLA %s
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- ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK, VLA %s
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+ ; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck -check-prefix= VLA %s
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+ ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck -check-prefix= VLA %s
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- ; RUN: llc < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK, VLS %s
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- ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefixes=CHECK, VLS %s
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+ ; RUN: llc < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefix= VLS %s
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+ ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -verify-machineinstrs | FileCheck -check-prefix= VLS %s
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define <8 x i32 > @concat_2xv4i32 (<4 x i32 > %a , <4 x i32 > %b ) {
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; VLA-LABEL: concat_2xv4i32:
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