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[RISCV] Add coverage for an upcoming set of vector narrowing changes
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4 files changed

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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,3 +148,54 @@ define void @abs_v4i64(ptr %x) {
148148
ret void
149149
}
150150
declare <4 x i64> @llvm.abs.v4i64(<4 x i64>, i1)
151+
152+
define void @abs_v4i64_of_sext_v4i8(ptr %x) {
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; CHECK-LABEL: abs_v4i64_of_sext_v4i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsext.vf8 v10, v8
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: vse64.v v8, (a0)
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; CHECK-NEXT: ret
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%a = load <4 x i8>, ptr %x
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%a.ext = sext <4 x i8> %a to <4 x i64>
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%b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false)
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store <4 x i64> %b, ptr %x
166+
ret void
167+
}
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169+
define void @abs_v4i64_of_sext_v4i16(ptr %x) {
170+
; CHECK-LABEL: abs_v4i64_of_sext_v4i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vsext.vf4 v10, v8
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: vse64.v v8, (a0)
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; CHECK-NEXT: ret
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%a = load <4 x i16>, ptr %x
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%a.ext = sext <4 x i16> %a to <4 x i64>
181+
%b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false)
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store <4 x i64> %b, ptr %x
183+
ret void
184+
}
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186+
define void @abs_v4i64_of_sext_v4i32(ptr %x) {
187+
; CHECK-LABEL: abs_v4i64_of_sext_v4i32:
188+
; CHECK: # %bb.0:
189+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsext.vf2 v10, v8
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: vse64.v v8, (a0)
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; CHECK-NEXT: ret
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%a = load <4 x i32>, ptr %x
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%a.ext = sext <4 x i32> %a to <4 x i64>
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%b = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %a.ext, i1 false)
199+
store <4 x i64> %b, ptr %x
200+
ret void
201+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -880,3 +880,57 @@ define <2 x i64> @vwadd_vx_v2i64_i64(ptr %x, ptr %y) nounwind {
880880
%g = add <2 x i64> %e, %f
881881
ret <2 x i64> %g
882882
}
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define <2 x i32> @vwadd_v2i32_of_v2i8(ptr %x, ptr %y) {
885+
; CHECK-LABEL: vwadd_v2i32_of_v2i8:
886+
; CHECK: # %bb.0:
887+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
888+
; CHECK-NEXT: vle8.v v8, (a1)
889+
; CHECK-NEXT: vle8.v v9, (a0)
890+
; CHECK-NEXT: vsext.vf2 v10, v8
891+
; CHECK-NEXT: vsext.vf2 v11, v9
892+
; CHECK-NEXT: vwadd.vv v8, v11, v10
893+
; CHECK-NEXT: ret
894+
%a = load <2 x i8>, ptr %x
895+
%b = load <2 x i8>, ptr %y
896+
%c = sext <2 x i8> %a to <2 x i32>
897+
%d = sext <2 x i8> %b to <2 x i32>
898+
%e = add <2 x i32> %c, %d
899+
ret <2 x i32> %e
900+
}
901+
902+
define <2 x i64> @vwadd_v2i64_of_v2i8(ptr %x, ptr %y) {
903+
; CHECK-LABEL: vwadd_v2i64_of_v2i8:
904+
; CHECK: # %bb.0:
905+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
906+
; CHECK-NEXT: vle8.v v8, (a1)
907+
; CHECK-NEXT: vle8.v v9, (a0)
908+
; CHECK-NEXT: vsext.vf4 v10, v8
909+
; CHECK-NEXT: vsext.vf4 v11, v9
910+
; CHECK-NEXT: vwadd.vv v8, v11, v10
911+
; CHECK-NEXT: ret
912+
%a = load <2 x i8>, ptr %x
913+
%b = load <2 x i8>, ptr %y
914+
%c = sext <2 x i8> %a to <2 x i64>
915+
%d = sext <2 x i8> %b to <2 x i64>
916+
%e = add <2 x i64> %c, %d
917+
ret <2 x i64> %e
918+
}
919+
920+
define <2 x i64> @vwadd_v2i64_of_v2i16(ptr %x, ptr %y) {
921+
; CHECK-LABEL: vwadd_v2i64_of_v2i16:
922+
; CHECK: # %bb.0:
923+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
924+
; CHECK-NEXT: vle16.v v8, (a1)
925+
; CHECK-NEXT: vle16.v v9, (a0)
926+
; CHECK-NEXT: vsext.vf2 v10, v8
927+
; CHECK-NEXT: vsext.vf2 v11, v9
928+
; CHECK-NEXT: vwadd.vv v8, v11, v10
929+
; CHECK-NEXT: ret
930+
%a = load <2 x i16>, ptr %x
931+
%b = load <2 x i16>, ptr %y
932+
%c = sext <2 x i16> %a to <2 x i64>
933+
%d = sext <2 x i16> %b to <2 x i64>
934+
%e = add <2 x i64> %c, %d
935+
ret <2 x i64> %e
936+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -908,3 +908,57 @@ define <4 x i64> @crash(<4 x i16> %x, <4 x i16> %y) {
908908
%c = add <4 x i64> %a, %b
909909
ret <4 x i64> %c
910910
}
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912+
define <2 x i32> @vwaddu_v2i32_of_v2i8(ptr %x, ptr %y) {
913+
; CHECK-LABEL: vwaddu_v2i32_of_v2i8:
914+
; CHECK: # %bb.0:
915+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
916+
; CHECK-NEXT: vle8.v v8, (a1)
917+
; CHECK-NEXT: vle8.v v9, (a0)
918+
; CHECK-NEXT: vzext.vf2 v10, v8
919+
; CHECK-NEXT: vzext.vf2 v11, v9
920+
; CHECK-NEXT: vwaddu.vv v8, v11, v10
921+
; CHECK-NEXT: ret
922+
%a = load <2 x i8>, ptr %x
923+
%b = load <2 x i8>, ptr %y
924+
%c = zext <2 x i8> %a to <2 x i32>
925+
%d = zext <2 x i8> %b to <2 x i32>
926+
%e = add <2 x i32> %c, %d
927+
ret <2 x i32> %e
928+
}
929+
930+
define <2 x i64> @vwaddu_v2i64_of_v2i8(ptr %x, ptr %y) {
931+
; CHECK-LABEL: vwaddu_v2i64_of_v2i8:
932+
; CHECK: # %bb.0:
933+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
934+
; CHECK-NEXT: vle8.v v8, (a1)
935+
; CHECK-NEXT: vle8.v v9, (a0)
936+
; CHECK-NEXT: vzext.vf4 v10, v8
937+
; CHECK-NEXT: vzext.vf4 v11, v9
938+
; CHECK-NEXT: vwaddu.vv v8, v11, v10
939+
; CHECK-NEXT: ret
940+
%a = load <2 x i8>, ptr %x
941+
%b = load <2 x i8>, ptr %y
942+
%c = zext <2 x i8> %a to <2 x i64>
943+
%d = zext <2 x i8> %b to <2 x i64>
944+
%e = add <2 x i64> %c, %d
945+
ret <2 x i64> %e
946+
}
947+
948+
define <2 x i64> @vwaddu_v2i64_of_v2i16(ptr %x, ptr %y) {
949+
; CHECK-LABEL: vwaddu_v2i64_of_v2i16:
950+
; CHECK: # %bb.0:
951+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
952+
; CHECK-NEXT: vle16.v v8, (a1)
953+
; CHECK-NEXT: vle16.v v9, (a0)
954+
; CHECK-NEXT: vzext.vf2 v10, v8
955+
; CHECK-NEXT: vzext.vf2 v11, v9
956+
; CHECK-NEXT: vwaddu.vv v8, v11, v10
957+
; CHECK-NEXT: ret
958+
%a = load <2 x i16>, ptr %x
959+
%b = load <2 x i16>, ptr %y
960+
%c = zext <2 x i16> %a to <2 x i64>
961+
%d = zext <2 x i16> %b to <2 x i64>
962+
%e = add <2 x i64> %c, %d
963+
ret <2 x i64> %e
964+
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -895,3 +895,57 @@ define <2 x i64> @vwsubu_vx_v2i64_i64(ptr %x, ptr %y) nounwind {
895895
%g = sub <2 x i64> %e, %f
896896
ret <2 x i64> %g
897897
}
898+
899+
define <2 x i32> @vwsubu_v2i32_of_v2i8(ptr %x, ptr %y) {
900+
; CHECK-LABEL: vwsubu_v2i32_of_v2i8:
901+
; CHECK: # %bb.0:
902+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
903+
; CHECK-NEXT: vle8.v v8, (a1)
904+
; CHECK-NEXT: vle8.v v9, (a0)
905+
; CHECK-NEXT: vzext.vf2 v10, v8
906+
; CHECK-NEXT: vzext.vf2 v11, v9
907+
; CHECK-NEXT: vwsubu.vv v8, v11, v10
908+
; CHECK-NEXT: ret
909+
%a = load <2 x i8>, ptr %x
910+
%b = load <2 x i8>, ptr %y
911+
%c = zext <2 x i8> %a to <2 x i32>
912+
%d = zext <2 x i8> %b to <2 x i32>
913+
%e = sub <2 x i32> %c, %d
914+
ret <2 x i32> %e
915+
}
916+
917+
define <2 x i64> @vwsubu_v2i64_of_v2i8(ptr %x, ptr %y) {
918+
; CHECK-LABEL: vwsubu_v2i64_of_v2i8:
919+
; CHECK: # %bb.0:
920+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
921+
; CHECK-NEXT: vle8.v v8, (a1)
922+
; CHECK-NEXT: vle8.v v9, (a0)
923+
; CHECK-NEXT: vzext.vf4 v10, v8
924+
; CHECK-NEXT: vzext.vf4 v11, v9
925+
; CHECK-NEXT: vwsubu.vv v8, v11, v10
926+
; CHECK-NEXT: ret
927+
%a = load <2 x i8>, ptr %x
928+
%b = load <2 x i8>, ptr %y
929+
%c = zext <2 x i8> %a to <2 x i64>
930+
%d = zext <2 x i8> %b to <2 x i64>
931+
%e = sub <2 x i64> %c, %d
932+
ret <2 x i64> %e
933+
}
934+
935+
define <2 x i64> @vwsubu_v2i64_of_v2i16(ptr %x, ptr %y) {
936+
; CHECK-LABEL: vwsubu_v2i64_of_v2i16:
937+
; CHECK: # %bb.0:
938+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
939+
; CHECK-NEXT: vle16.v v8, (a1)
940+
; CHECK-NEXT: vle16.v v9, (a0)
941+
; CHECK-NEXT: vzext.vf2 v10, v8
942+
; CHECK-NEXT: vzext.vf2 v11, v9
943+
; CHECK-NEXT: vwsubu.vv v8, v11, v10
944+
; CHECK-NEXT: ret
945+
%a = load <2 x i16>, ptr %x
946+
%b = load <2 x i16>, ptr %y
947+
%c = zext <2 x i16> %a to <2 x i64>
948+
%d = zext <2 x i16> %b to <2 x i64>
949+
%e = sub <2 x i64> %c, %d
950+
ret <2 x i64> %e
951+
}

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