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davemgreendavemgreen
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[GlobalISel][AArch64] Add LLRINT support (#88702)
This hooks up G_INTRINSIC_LLRINT instructions, very similar to the lrint nodes that already exist. On AArch64 they are treated the same as lrint with the default return types.
1 parent d423d80 commit 8d49ce1

18 files changed

+251
-104
lines changed

‎llvm/include/llvm/Support/TargetOpcodes.def

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -351,6 +351,9 @@ HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
351351
/// INTRINSIC round to integer intrinsic.
352352
HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT)
353353

354+
/// INTRINSIC long round to integer intrinsic.
355+
HANDLE_TARGET_OPCODE(G_INTRINSIC_LLRINT)
356+
354357
/// INTRINSIC roundeven intrinsic.
355358
HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN)
356359

‎llvm/include/llvm/Target/GenericOpcodes.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1089,6 +1089,12 @@ def G_INTRINSIC_LRINT : GenericInstruction {
10891089
let hasSideEffects = false;
10901090
}
10911091

1092+
def G_INTRINSIC_LLRINT : GenericInstruction {
1093+
let OutOperandList = (outs type0:$dst);
1094+
let InOperandList = (ins type1:$src);
1095+
let hasSideEffects = false;
1096+
}
1097+
10921098
def G_INTRINSIC_ROUNDEVEN : GenericInstruction {
10931099
let OutOperandList = (outs type0:$dst);
10941100
let InOperandList = (ins type0:$src1);

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,7 @@ def : GINodeEquiv<G_INTRINSIC_TRUNC, ftrunc>;
157157
def : GINodeEquiv<G_INTRINSIC_ROUND, fround>;
158158
def : GINodeEquiv<G_INTRINSIC_ROUNDEVEN, froundeven>;
159159
def : GINodeEquiv<G_INTRINSIC_LRINT, lrint>;
160+
def : GINodeEquiv<G_INTRINSIC_LLRINT, llrint>;
160161
def : GINodeEquiv<G_FCOPYSIGN, fcopysign>;
161162
def : GINodeEquiv<G_SMIN, smin>;
162163
def : GINodeEquiv<G_SMAX, smax>;

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1955,6 +1955,8 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
19551955
return TargetOpcode::G_PTRMASK;
19561956
case Intrinsic::lrint:
19571957
return TargetOpcode::G_INTRINSIC_LRINT;
1958+
case Intrinsic::llrint:
1959+
return TargetOpcode::G_INTRINSIC_LLRINT;
19581960
// FADD/FMUL require checking the FMF, so are handled elsewhere.
19591961
case Intrinsic::vector_reduce_fmin:
19601962
return TargetOpcode::G_VECREDUCE_FMIN;

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -474,6 +474,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
474474
RTLIBCASE(ROUNDEVEN_F);
475475
case TargetOpcode::G_INTRINSIC_LRINT:
476476
RTLIBCASE(LRINT_F);
477+
case TargetOpcode::G_INTRINSIC_LLRINT:
478+
RTLIBCASE(LLRINT_F);
477479
}
478480
llvm_unreachable("Unknown libcall function");
479481
}
@@ -1061,7 +1063,8 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
10611063
return Status;
10621064
break;
10631065
}
1064-
case TargetOpcode::G_INTRINSIC_LRINT: {
1066+
case TargetOpcode::G_INTRINSIC_LRINT:
1067+
case TargetOpcode::G_INTRINSIC_LLRINT: {
10651068
LLT LLTy = MRI.getType(MI.getOperand(1).getReg());
10661069
unsigned Size = LLTy.getSizeInBits();
10671070
Type *HLTy = getFloatTypeForLLT(Ctx, LLTy);
@@ -2661,6 +2664,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
26612664
case TargetOpcode::G_FPTOSI:
26622665
case TargetOpcode::G_FPTOUI:
26632666
case TargetOpcode::G_INTRINSIC_LRINT:
2667+
case TargetOpcode::G_INTRINSIC_LLRINT:
26642668
case TargetOpcode::G_IS_FPCLASS:
26652669
Observer.changingInstr(MI);
26662670

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -262,7 +262,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
262262
.minScalar(0, s32)
263263
.scalarize(0);
264264

265-
getActionDefinitionsBuilder(G_INTRINSIC_LRINT)
265+
getActionDefinitionsBuilder({G_INTRINSIC_LRINT, G_INTRINSIC_LLRINT})
266266
.legalFor({{s64, MinFPScalar}, {s64, s32}, {s64, s64}})
267267
.libcallFor({{s64, s128}})
268268
.minScalarOrElt(1, MinFPScalar);

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -793,6 +793,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
793793
case TargetOpcode::G_FPTOSI:
794794
case TargetOpcode::G_FPTOUI:
795795
case TargetOpcode::G_INTRINSIC_LRINT:
796+
case TargetOpcode::G_INTRINSIC_LLRINT:
796797
if (MRI.getType(MI.getOperand(0).getReg()).isVector())
797798
break;
798799
OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1385,6 +1385,16 @@ define i32 @test_intrinsic_lrint(float %a) {
13851385
ret i32 %res
13861386
}
13871387

1388+
declare i32 @llvm.llrint.i32.f32(float)
1389+
define i32 @test_intrinsic_llrint(float %a) {
1390+
; CHECK-LABEL: name: test_intrinsic_llrint
1391+
; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
1392+
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_LLRINT [[A]]
1393+
; CHECK: $w0 = COPY [[RES]]
1394+
%res = call i32 @llvm.llrint.i32.f32(float %a)
1395+
ret i32 %res
1396+
}
1397+
13881398
declare i32 @llvm.ctlz.i32(i32, i1)
13891399
define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
13901400
; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-llrint.mir

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer %s -o - | FileCheck %s
3+
---
4+
name: testmsws
5+
alignment: 4
6+
tracksRegLiveness: true
7+
liveins:
8+
- { reg: '$s0' }
9+
body: |
10+
bb.1:
11+
liveins: $s0
12+
13+
; CHECK-LABEL: name: testmsws
14+
; CHECK: liveins: $s0
15+
; CHECK-NEXT: {{ $}}
16+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
17+
; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s32)
18+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[INTRINSIC_LLRINT]](s64)
19+
; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
20+
; CHECK-NEXT: RET_ReallyLR implicit $w0
21+
%0:_(s32) = COPY $s0
22+
%1:_(s64) = G_INTRINSIC_LLRINT %0(s32)
23+
%2:_(s32) = G_TRUNC %1(s64)
24+
$w0 = COPY %2(s32)
25+
RET_ReallyLR implicit $w0
26+
27+
...
28+
---
29+
name: testmsxs
30+
alignment: 4
31+
tracksRegLiveness: true
32+
liveins:
33+
- { reg: '$s0' }
34+
body: |
35+
bb.1:
36+
liveins: $s0
37+
38+
; CHECK-LABEL: name: testmsxs
39+
; CHECK: liveins: $s0
40+
; CHECK-NEXT: {{ $}}
41+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
42+
; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s32)
43+
; CHECK-NEXT: $x0 = COPY [[INTRINSIC_LLRINT]](s64)
44+
; CHECK-NEXT: RET_ReallyLR implicit $x0
45+
%0:_(s32) = COPY $s0
46+
%1:_(s64) = G_INTRINSIC_LLRINT %0(s32)
47+
$x0 = COPY %1(s64)
48+
RET_ReallyLR implicit $x0
49+
50+
...
51+
---
52+
name: testmswd
53+
alignment: 4
54+
tracksRegLiveness: true
55+
liveins:
56+
- { reg: '$d0' }
57+
body: |
58+
bb.1:
59+
liveins: $d0
60+
61+
; CHECK-LABEL: name: testmswd
62+
; CHECK: liveins: $d0
63+
; CHECK-NEXT: {{ $}}
64+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
65+
; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s64)
66+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[INTRINSIC_LLRINT]](s64)
67+
; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
68+
; CHECK-NEXT: RET_ReallyLR implicit $w0
69+
%0:_(s64) = COPY $d0
70+
%1:_(s64) = G_INTRINSIC_LLRINT %0(s64)
71+
%2:_(s32) = G_TRUNC %1(s64)
72+
$w0 = COPY %2(s32)
73+
RET_ReallyLR implicit $w0
74+
75+
...
76+
---
77+
name: testmsxd
78+
alignment: 4
79+
tracksRegLiveness: true
80+
liveins:
81+
- { reg: '$d0' }
82+
body: |
83+
bb.1:
84+
liveins: $d0
85+
86+
; CHECK-LABEL: name: testmsxd
87+
; CHECK: liveins: $d0
88+
; CHECK-NEXT: {{ $}}
89+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
90+
; CHECK-NEXT: [[INTRINSIC_LLRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LLRINT [[COPY]](s64)
91+
; CHECK-NEXT: $x0 = COPY [[INTRINSIC_LLRINT]](s64)
92+
; CHECK-NEXT: RET_ReallyLR implicit $x0
93+
%0:_(s64) = COPY $d0
94+
%1:_(s64) = G_INTRINSIC_LLRINT %0(s64)
95+
$x0 = COPY %1(s64)
96+
RET_ReallyLR implicit $x0
97+
98+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,10 @@
156156
# DEBUG-NEXT: G_INTRINSIC_LRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
157157
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
158158
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
159+
# DEBUG-NEXT: G_INTRINSIC_LLRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
160+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
161+
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
162+
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
159163
# DEBUG-NEXT: G_INTRINSIC_ROUNDEVEN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
160164
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
161165
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected

‎llvm/test/CodeGen/AArch64/llrint-conv-fp16.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16
33
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16
4+
; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK-NOFP16
5+
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK-FP16
46

57
define i16 @testmhhs(half %x) {
68
; CHECK-NOFP16-LABEL: testmhhs:

‎llvm/test/CodeGen/AArch64/llrint-conv.ll

Lines changed: 37 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,59 +1,75 @@
1-
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2+
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
3+
; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s
24

3-
; CHECK-LABEL: testmsws:
4-
; CHECK: frintx [[REG:s[0-9]]], s0
5-
; CHECK-NEXT: fcvtzs x0, [[REG]]
6-
; CHECK: ret
75
define i32 @testmsws(float %x) {
6+
; CHECK-LABEL: testmsws:
7+
; CHECK: // %bb.0: // %entry
8+
; CHECK-NEXT: frintx s0, s0
9+
; CHECK-NEXT: fcvtzs x0, s0
10+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
11+
; CHECK-NEXT: ret
812
entry:
913
%0 = tail call i64 @llvm.llrint.f32(float %x)
1014
%conv = trunc i64 %0 to i32
1115
ret i32 %conv
1216
}
1317

14-
; CHECK-LABEL: testmsxs:
15-
; CHECK: frintx [[REG:s[0-9]]], s0
16-
; CHECK-NEXT: fcvtzs x0, [[REG]]
17-
; CHECK-NEXT: ret
1818
define i64 @testmsxs(float %x) {
19+
; CHECK-LABEL: testmsxs:
20+
; CHECK: // %bb.0: // %entry
21+
; CHECK-NEXT: frintx s0, s0
22+
; CHECK-NEXT: fcvtzs x0, s0
23+
; CHECK-NEXT: ret
1924
entry:
2025
%0 = tail call i64 @llvm.llrint.f32(float %x)
2126
ret i64 %0
2227
}
2328

24-
; CHECK-LABEL: testmswd:
25-
; CHECK: frintx [[REG:d[0-9]]], d0
26-
; CHECK-NEXT: fcvtzs x0, [[REG]]
27-
; CHECK: ret
2829
define i32 @testmswd(double %x) {
30+
; CHECK-LABEL: testmswd:
31+
; CHECK: // %bb.0: // %entry
32+
; CHECK-NEXT: frintx d0, d0
33+
; CHECK-NEXT: fcvtzs x0, d0
34+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
35+
; CHECK-NEXT: ret
2936
entry:
3037
%0 = tail call i64 @llvm.llrint.f64(double %x)
3138
%conv = trunc i64 %0 to i32
3239
ret i32 %conv
3340
}
3441

35-
; CHECK-LABEL: testmsxd:
36-
; CHECK: frintx [[REG:d[0-9]]], d0
37-
; CHECK-NEXT: fcvtzs x0, [[REG]]
38-
; CHECK-nEXT: ret
3942
define i64 @testmsxd(double %x) {
43+
; CHECK-LABEL: testmsxd:
44+
; CHECK: // %bb.0: // %entry
45+
; CHECK-NEXT: frintx d0, d0
46+
; CHECK-NEXT: fcvtzs x0, d0
47+
; CHECK-NEXT: ret
4048
entry:
4149
%0 = tail call i64 @llvm.llrint.f64(double %x)
4250
ret i64 %0
4351
}
4452

45-
; CHECK-LABEL: testmswl:
46-
; CHECK: bl llrintl
4753
define i32 @testmswl(fp128 %x) {
54+
; CHECK-LABEL: testmswl:
55+
; CHECK: // %bb.0: // %entry
56+
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
57+
; CHECK-NEXT: .cfi_def_cfa_offset 16
58+
; CHECK-NEXT: .cfi_offset w30, -16
59+
; CHECK-NEXT: bl llrintl
60+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
61+
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
62+
; CHECK-NEXT: ret
4863
entry:
4964
%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
5065
%conv = trunc i64 %0 to i32
5166
ret i32 %conv
5267
}
5368

54-
; CHECK-LABEL: testmsll:
55-
; CHECK: b llrintl
5669
define i64 @testmsll(fp128 %x) {
70+
; CHECK-LABEL: testmsll:
71+
; CHECK: // %bb.0: // %entry
72+
; CHECK-NEXT: b llrintl
5773
entry:
5874
%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
5975
ret i64 %0

‎llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -28,11 +28,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
2828

2929
// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const {
3030
// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = {
31-
// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(69), GIMT_Encode2(186), /*)*//*default:*//*Label 2*/ GIMT_Encode4(562),
32-
// CHECK-NEXT: /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ GIMT_Encode4(478), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
33-
// CHECK-NEXT: /*TargetOpcode::G_FNEG*//*Label 1*/ GIMT_Encode4(530),
34-
// CHECK-NEXT: // Label 0: @478
35-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(529), // Rule ID 1 //
31+
// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label 2*/ GIMT_Encode4([[L562:[0-9]+]]),
32+
// CHECK-NEXT: /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ GIMT_Encode4([[L478:[0-9]+]]), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
33+
// CHECK-NEXT: /*TargetOpcode::G_FNEG*//*Label 1*/ GIMT_Encode4([[L530:[0-9]+]]),
34+
// CHECK-NEXT: // Label 0: @[[L478]]
35+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4([[L529:[0-9]+]]), // Rule ID 1 //
3636
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled),
3737
// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
3838
// CHECK-NEXT: // MIs[0] a
@@ -57,10 +57,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
5757
// CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0,
5858
// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
5959
// CHECK-NEXT: GIR_Done,
60-
// CHECK-NEXT: // Label 3: @529
60+
// CHECK-NEXT: // Label 3: @[[L529]]
6161
// CHECK-NEXT: GIM_Reject,
62-
// CHECK-NEXT: // Label 1: @530
63-
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(561), // Rule ID 0 //
62+
// CHECK-NEXT: // Label 1: @[[L530]]
63+
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4([[L561:[0-9]+]]), // Rule ID 0 //
6464
// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled),
6565
// CHECK-NEXT: // MIs[0] dst
6666
// CHECK-NEXT: // No operand predicates
@@ -75,10 +75,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [
7575
// CHECK-NEXT: GIR_ReplaceReg, /*OldInsnID*/0, /*OldOpIdx*/0, /*NewInsnId*/1, /*NewOpIdx*/1,
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK-NEXT: GIR_Done,
78-
// CHECK-NEXT: // Label 4: @561
78+
// CHECK-NEXT: // Label 4: @[[L561]]
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// CHECK-NEXT: GIM_Reject,
80-
// CHECK-NEXT: // Label 2: @562
80+
// CHECK-NEXT: // Label 2: @[[L562]]
8181
// CHECK-NEXT: GIM_Reject,
82-
// CHECK-NEXT: }; // Size: 563 bytes
82+
// CHECK-NEXT: }; // Size: {{[0-9]+}} bytes
8383
// CHECK-NEXT: return MatchTable0;
8484
// CHECK-NEXT: }

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