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[RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (#144320)
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. The instructions are similar to `Zvfbfmin` and the only difference with `Zvfbfmin` is that `XAndesVBFHCvt` doesn't have mask variant.
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -159,6 +159,7 @@
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// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
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// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
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// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
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// CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)
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// CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension)
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// CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension)
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// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)

‎clang/test/Preprocessor/riscv-target-features-andes.c

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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESPERF %s
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// CHECK-XANDESPERF: __riscv_xandesperf 5000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32i_xandesvbfhcvt -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64i_xandesvbfhcvt -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
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// CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt 5000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32i_xandesvpackfph -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVPACKFPH %s

‎llvm/docs/RISCVUsage.rst

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@@ -513,6 +513,9 @@ The current vendor extensions supported are:
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``XAndesPerf``
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LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XAndesVBFHCvt``
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LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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``XAndesVPackFPH``
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LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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‎llvm/docs/ReleaseNotes.md

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@@ -210,6 +210,7 @@ Changes to the RISC-V Backend
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* The `Shlcofideleg` extension was added.
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* `-mcpu=sifive-x390` was added.
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* `-mtune=andes-45-series` was added.
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* Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension).
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -774,8 +774,8 @@ static constexpr FeatureBitset XTHeadGroup = {
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RISCV::FeatureVendorXTHeadVdot};
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static constexpr FeatureBitset XAndesGroup = {
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RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVPackFPH,
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RISCV::FeatureVendorXAndesVDot};
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RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVBFHCvt,
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RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot};
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static constexpr DecoderListEntry DecoderList32[]{
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// Vendor Extensions

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1599,6 +1599,15 @@ def HasVendorXAndesPerf
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AssemblerPredicate<(all_of FeatureVendorXAndesPerf),
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"'XAndesPerf' (Andes Performance Extension)">;
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def FeatureVendorXAndesVBFHCvt
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: RISCVExtension<5, 0, "Andes Vector BFLOAT16 Conversion Extension",
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[FeatureStdExtZve32f]>;
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def HasVendorXAndesVBFHCvt
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: Predicate<"Subtarget->hasVendorXAndesVBFHCvt()">,
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AssemblerPredicate<(all_of FeatureVendorXAndesVBFHCvt),
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"'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">;
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def FeatureVendorXAndesVPackFPH
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: RISCVExtension<5, 0, "Andes Vector Packed FP16 Extension",
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[FeatureStdExtZvfhmin]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

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@@ -361,6 +361,25 @@ class NDSRVInstVD4DOT<bits<6> funct6, string opcodestr>
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let RVVConstraint = VMConstraint;
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}
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class NDSRVInstVBFHCvt<bits<7> funct7, bits<5> vs1, string opcodestr>
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: RVInst<(outs VR:$vd), (ins VR:$vs2, VMaskOp:$vm),
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opcodestr, "$vd, $vs2", [], InstFormatR> {
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bits<5> vs2;
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bits<5> vd;
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let Inst{31-25} = funct7;
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let Inst{24-20} = vs2;
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let Inst{19-15} = vs1;
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let Inst{14-12} = 0b100;
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let Inst{11-7} = vd;
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let Inst{6-0} = OPC_CUSTOM_2.Value;
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 0;
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let Uses = [VL, VTYPE];
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}
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//===----------------------------------------------------------------------===//
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// Multiclass
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//===----------------------------------------------------------------------===//
@@ -460,6 +479,18 @@ def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">;
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def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">;
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} // Predicates = [HasVendorXAndesPerf, IsRV64]
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//===----------------------------------------------------------------------===//
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// XAndesVBFHCvt
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXAndesVBFHCvt], Constraints = "@earlyclobber $vd",
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mayRaiseFPException = true in {
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let RVVConstraint = VS2Constraint, DestEEW = EEWSEWx2 in
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def NDS_VFWCVT_S_BF16 : NDSRVInstVBFHCvt<0b0000000, 0b00000, "nds.vfwcvt.s.bf16">;
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let Uses = [FRM, VL, VTYPE] in
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def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b0000000, 0b00001, "nds.vfncvt.bf16.s">;
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}
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//===----------------------------------------------------------------------===//
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// XAndesVPackFPH
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/attributes.ll

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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s
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; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s
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; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s
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; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s
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; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s
@@ -457,6 +459,7 @@
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; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
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; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p3"
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; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0"
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; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
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; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
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; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
@@ -612,6 +615,7 @@
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; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0"
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; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
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; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0"
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; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
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; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
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; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
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; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0"

‎llvm/test/CodeGen/RISCV/features-info.ll

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; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors.
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; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush.
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; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension).
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; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension).
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; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension).
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; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension).
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; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations).

‎llvm/test/MC/RISCV/xandesvbfhcvt-valid.s

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# XAndesVBFHCvt - Andes Vector BFLOAT16 Conversion Extension
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvbfhcvt -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvbfhcvt < %s \
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# RUN: | llvm-objdump --mattr=+xandesvbfhcvt -M no-aliases -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
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# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvbfhcvt -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvbfhcvt < %s \
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# RUN: | llvm-objdump --mattr=+xandesvbfhcvt -M no-aliases -d -r - \
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# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s
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# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
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# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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# CHECK-OBJ: nds.vfwcvt.s.bf16 v8, v10
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# CHECK-ASM: nds.vfwcvt.s.bf16 v8, v10
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# CHECK-ASM: encoding: [0x5b,0x44,0xa0,0x00]
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# CHECK-ERROR: instruction requires the following: 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension){{$}}
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nds.vfwcvt.s.bf16 v8, v10
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# CHECK-OBJ: nds.vfncvt.bf16.s v8, v10
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# CHECK-ASM: nds.vfncvt.bf16.s v8, v10
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# CHECK-ASM: encoding: [0x5b,0xc4,0xa0,0x00]
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# CHECK-ERROR: instruction requires the following: 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension){{$}}
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nds.vfncvt.bf16.s v8, v10

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1130,6 +1130,7 @@ R"(All available -march extensions for RISC-V
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svpbmt 1.0
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svvptc 1.0
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xandesperf 5.0
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xandesvbfhcvt 5.0
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xandesvdot 5.0
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xandesvpackfph 5.0
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xcvalu 1.0

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