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author
Kai Luo
committed
Update test checks
1 parent c5c7e28 commit 8e3f7f6

35 files changed

+1141
-1140
lines changed

‎llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -666,10 +666,11 @@ bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
666666
}
667667
llvm::copy_if(llvm::make_range(Order.begin(), Order.end()),
668668
std::back_inserter(Hints), [&](MCPhysReg Reg) {
669-
// if (TRI->regsOverlap(Reg, PPC::CR2) ||
670-
// TRI->regsOverlap(Reg, PPC::CR3) ||
671-
// TRI->regsOverlap(Reg, PPC::CR4))
672-
// return false;
669+
// Be conservative not to use callee saved CRs.
670+
if (TRI->regsOverlap(Reg, PPC::CR2) ||
671+
TRI->regsOverlap(Reg, PPC::CR3) ||
672+
TRI->regsOverlap(Reg, PPC::CR4))
673+
return false;
673674
return llvm::all_of(TRI->superregs_inclusive(Reg),
674675
[&](MCPhysReg SR) {
675676
return !ModifiedRegisters.count(SR);

‎llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,14 +25,14 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
2525
; CHECK-NEXT: fcmpu 1, 1, 27
2626
; CHECK-NEXT: lwz 3, 384(1)
2727
; CHECK-NEXT: crand 20, 6, 0
28-
; CHECK-NEXT: cror 20, 4, 20
28+
; CHECK-NEXT: cror 24, 4, 20
2929
; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill
3030
; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill
3131
; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill
3232
; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill
3333
; CHECK-NEXT: stw 4, 404(1)
3434
; CHECK-NEXT: stw 3, 400(1)
35-
; CHECK-NEXT: bc 4, 20, .LBB0_2
35+
; CHECK-NEXT: bc 4, 24, .LBB0_2
3636
; CHECK-NEXT: # %bb.1: # %bb5
3737
; CHECK-NEXT: li 3, 0
3838
; CHECK-NEXT: li 4, 0
@@ -106,9 +106,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
106106
; CHECK-NEXT: fcmpu 1, 29, 0
107107
; CHECK-NEXT: lwz 4, 156(1)
108108
; CHECK-NEXT: crandc 20, 6, 0
109-
; CHECK-NEXT: cror 20, 5, 20
109+
; CHECK-NEXT: cror 24, 5, 20
110110
; CHECK-NEXT: addis 3, 3, -32768
111-
; CHECK-NEXT: bc 12, 20, .LBB0_4
111+
; CHECK-NEXT: bc 12, 24, .LBB0_4
112112
; CHECK-NEXT: # %bb.3: # %bb1
113113
; CHECK-NEXT: ori 30, 4, 0
114114
; CHECK-NEXT: b .LBB0_5
@@ -230,9 +230,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
230230
; CHECK-NEXT: fcmpu 1, 31, 0
231231
; CHECK-NEXT: lwz 4, 28(1)
232232
; CHECK-NEXT: crandc 20, 6, 1
233-
; CHECK-NEXT: cror 20, 4, 20
233+
; CHECK-NEXT: cror 24, 4, 20
234234
; CHECK-NEXT: addis 3, 3, -32768
235-
; CHECK-NEXT: bc 12, 20, .LBB0_13
235+
; CHECK-NEXT: bc 12, 24, .LBB0_13
236236
; CHECK-NEXT: # %bb.12: # %bb2
237237
; CHECK-NEXT: ori 3, 4, 0
238238
; CHECK-NEXT: b .LBB0_13
@@ -285,9 +285,9 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
285285
; CHECK-NEXT: fcmpu 1, 31, 0
286286
; CHECK-NEXT: lwz 4, 92(1)
287287
; CHECK-NEXT: crandc 20, 6, 0
288-
; CHECK-NEXT: cror 20, 5, 20
288+
; CHECK-NEXT: cror 24, 5, 20
289289
; CHECK-NEXT: addis 3, 3, -32768
290-
; CHECK-NEXT: bc 12, 20, .LBB0_15
290+
; CHECK-NEXT: bc 12, 24, .LBB0_15
291291
; CHECK-NEXT: b .LBB0_16
292292
; CHECK-NEXT: .LBB0_15: # %bb3
293293
; CHECK-NEXT: addi 4, 3, 0

‎llvm/test/CodeGen/PowerPC/all-atomics.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5687,14 +5687,14 @@ define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) loc
56875687
; AIX32-NEXT: cmplw 5, 30
56885688
; AIX32-NEXT: cmpw 1, 5, 30
56895689
; AIX32-NEXT: li 7, 5
5690-
; AIX32-NEXT: li 8, 5
5690+
; AIX32-NEXT: cmplw 6, 4, 31
56915691
; AIX32-NEXT: stw 5, 56(1)
56925692
; AIX32-NEXT: mr 3, 29
56935693
; AIX32-NEXT: crandc 20, 5, 2
5694-
; AIX32-NEXT: cmplw 1, 4, 31
5695-
; AIX32-NEXT: crand 21, 2, 5
5694+
; AIX32-NEXT: crand 28, 2, 25
5695+
; AIX32-NEXT: li 8, 5
56965696
; AIX32-NEXT: stw 4, 60(1)
5697-
; AIX32-NEXT: cror 20, 21, 20
5697+
; AIX32-NEXT: cror 20, 28, 20
56985698
; AIX32-NEXT: isel 5, 5, 30, 20
56995699
; AIX32-NEXT: isel 6, 4, 31, 20
57005700
; AIX32-NEXT: mr 4, 28
@@ -5708,15 +5708,15 @@ define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) loc
57085708
; AIX32-NEXT: cmplw 5, 30
57095709
; AIX32-NEXT: cmpw 1, 5, 30
57105710
; AIX32-NEXT: li 3, 55
5711+
; AIX32-NEXT: cmplw 6, 4, 31
5712+
; AIX32-NEXT: lwz 31, 76(1) # 4-byte Folded Reload
57115713
; AIX32-NEXT: lwz 30, 72(1) # 4-byte Folded Reload
57125714
; AIX32-NEXT: lwz 29, 68(1) # 4-byte Folded Reload
57135715
; AIX32-NEXT: lwz 28, 64(1) # 4-byte Folded Reload
57145716
; AIX32-NEXT: crandc 20, 5, 2
5715-
; AIX32-NEXT: cmplw 1, 4, 31
5717+
; AIX32-NEXT: crand 28, 2, 25
57165718
; AIX32-NEXT: li 4, 66
5717-
; AIX32-NEXT: lwz 31, 76(1) # 4-byte Folded Reload
5718-
; AIX32-NEXT: crand 21, 2, 5
5719-
; AIX32-NEXT: cror 20, 21, 20
5719+
; AIX32-NEXT: cror 20, 28, 20
57205720
; AIX32-NEXT: isel 4, 4, 3, 20
57215721
; AIX32-NEXT: li 3, 0
57225722
; AIX32-NEXT: addi 1, 1, 80

‎llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -9,24 +9,24 @@
99
; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
1010

1111
define dso_local signext i32 @test_builtin_ppc_cmprb(i32 %a, i32%b, i32 %c, i32%d) {
12-
; CHECK-32-LABEL: test_builtin_ppc_cmprb:
13-
; CHECK-32: # %bb.0: # %entry
14-
; CHECK-32-NEXT: cmprb 0, 0, 3, 4
15-
; CHECK-32-NEXT: setb 3, 0
16-
; CHECK-32-NEXT: cmprb 0, 1, 5, 6
17-
; CHECK-32-NEXT: setb 4, 0
18-
; CHECK-32-NEXT: add 3, 3, 4
19-
; CHECK-32-NEXT: blr
20-
;
2112
; CHECK-64-LABEL: test_builtin_ppc_cmprb:
2213
; CHECK-64: # %bb.0: # %entry
2314
; CHECK-64-NEXT: cmprb 0, 0, 3, 4
15+
; CHECK-64-NEXT: cmprb 1, 1, 5, 6
2416
; CHECK-64-NEXT: setb 3, 0
25-
; CHECK-64-NEXT: cmprb 0, 1, 5, 6
26-
; CHECK-64-NEXT: setb 4, 0
17+
; CHECK-64-NEXT: setb 4, 1
2718
; CHECK-64-NEXT: add 3, 3, 4
2819
; CHECK-64-NEXT: extsw 3, 3
2920
; CHECK-64-NEXT: blr
21+
;
22+
; CHECK-32-LABEL: test_builtin_ppc_cmprb:
23+
; CHECK-32: # %bb.0: # %entry
24+
; CHECK-32-NEXT: cmprb 0, 0, 3, 4
25+
; CHECK-32-NEXT: cmprb 1, 1, 5, 6
26+
; CHECK-32-NEXT: setb 3, 0
27+
; CHECK-32-NEXT: setb 4, 1
28+
; CHECK-32-NEXT: add 3, 3, 4
29+
; CHECK-32-NEXT: blr
3030
entry:
3131
%0 = call i32 @llvm.ppc.cmprb(i32 0, i32 %a, i32 %b)
3232
%1 = call i32 @llvm.ppc.cmprb(i32 1, i32 %c, i32 %d)

‎llvm/test/CodeGen/PowerPC/common-chain.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -753,8 +753,8 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64
753753
; CHECK-NEXT: iselgt r7, r6, r7
754754
; CHECK-NEXT: addi r8, r7, -1
755755
; CHECK-NEXT: clrldi r6, r7, 63
756-
; CHECK-NEXT: cmpldi r8, 3
757-
; CHECK-NEXT: blt cr0, .LBB7_4
756+
; CHECK-NEXT: cmpldi cr1, r8, 3
757+
; CHECK-NEXT: blt cr1, .LBB7_4
758758
; CHECK-NEXT: # %bb.2: # %for.body.preheader.new
759759
; CHECK-NEXT: ld r14, -168(r1) # 8-byte Folded Reload
760760
; CHECK-NEXT: mulli r24, r30, 24

‎llvm/test/CodeGen/PowerPC/crbit-asm.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,9 @@ define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
1616
; CHECK-NEXT: li 3, 0
1717
; CHECK-NEXT: li 4, 1
1818
; CHECK-NEXT: #APP
19-
; CHECK-NEXT: crand 20, 20, 1
19+
; CHECK-NEXT: crand 24, 20, 1
2020
; CHECK-NEXT: #NO_APP
21-
; CHECK-NEXT: isel 3, 4, 3, 20
21+
; CHECK-NEXT: isel 3, 4, 3, 24
2222
; CHECK-NEXT: blr
2323
;
2424
; CHECK-NO-ISEL-LABEL: testi1:
@@ -29,9 +29,9 @@ define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
2929
; CHECK-NO-ISEL-NEXT: li 3, 0
3030
; CHECK-NO-ISEL-NEXT: li 4, 1
3131
; CHECK-NO-ISEL-NEXT: #APP
32-
; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
32+
; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
3333
; CHECK-NO-ISEL-NEXT: #NO_APP
34-
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB0_1
34+
; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB0_1
3535
; CHECK-NO-ISEL-NEXT: blr
3636
; CHECK-NO-ISEL-NEXT: .LBB0_1: # %entry
3737
; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
@@ -53,9 +53,9 @@ define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
5353
; CHECK-NEXT: li 3, 0
5454
; CHECK-NEXT: li 4, -1
5555
; CHECK-NEXT: #APP
56-
; CHECK-NEXT: crand 20, 20, 1
56+
; CHECK-NEXT: crand 24, 20, 1
5757
; CHECK-NEXT: #NO_APP
58-
; CHECK-NEXT: isel 3, 4, 3, 20
58+
; CHECK-NEXT: isel 3, 4, 3, 24
5959
; CHECK-NEXT: blr
6060
;
6161
; CHECK-NO-ISEL-LABEL: testi32:
@@ -66,9 +66,9 @@ define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
6666
; CHECK-NO-ISEL-NEXT: li 3, 0
6767
; CHECK-NO-ISEL-NEXT: li 4, -1
6868
; CHECK-NO-ISEL-NEXT: #APP
69-
; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
69+
; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
7070
; CHECK-NO-ISEL-NEXT: #NO_APP
71-
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB1_1
71+
; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB1_1
7272
; CHECK-NO-ISEL-NEXT: blr
7373
; CHECK-NO-ISEL-NEXT: .LBB1_1: # %entry
7474
; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
@@ -91,9 +91,9 @@ define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
9191
; CHECK-NEXT: li 3, 0
9292
; CHECK-NEXT: li 4, 1
9393
; CHECK-NEXT: #APP
94-
; CHECK-NEXT: crand 20, 20, 1
94+
; CHECK-NEXT: crand 24, 20, 1
9595
; CHECK-NEXT: #NO_APP
96-
; CHECK-NEXT: isel 3, 4, 3, 20
96+
; CHECK-NEXT: isel 3, 4, 3, 24
9797
; CHECK-NEXT: blr
9898
;
9999
; CHECK-NO-ISEL-LABEL: testi8:
@@ -104,9 +104,9 @@ define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
104104
; CHECK-NO-ISEL-NEXT: li 3, 0
105105
; CHECK-NO-ISEL-NEXT: li 4, 1
106106
; CHECK-NO-ISEL-NEXT: #APP
107-
; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
107+
; CHECK-NO-ISEL-NEXT: crand 24, 20, 1
108108
; CHECK-NO-ISEL-NEXT: #NO_APP
109-
; CHECK-NO-ISEL-NEXT: bc 12, 20, .LBB2_1
109+
; CHECK-NO-ISEL-NEXT: bc 12, 24, .LBB2_1
110110
; CHECK-NO-ISEL-NEXT: blr
111111
; CHECK-NO-ISEL-NEXT: .LBB2_1: # %entry
112112
; CHECK-NO-ISEL-NEXT: addi 3, 4, 0

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