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[RISCV] Remove unnecessary vand.vi from vXi1 and nvXvi1 VECTOR_REVERSE codegen. (#109071)
Use a setne with 0 instead of a trunc. We know we zero extended the node so we can get by with a non-zero check only. The truncate lowering doesn't know that we zero extended so has to mask the lsb. I don't think DAG combine sees the trunc before we lower it to RISCVISD nodes so we don't get a chance to use computeKnownBits to remove the AND.
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2 files changed

+26
-61
lines changed

2 files changed

+26
-61
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10775,7 +10775,8 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
1077510775
MVT WidenVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorElementCount());
1077610776
SDValue Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, Op.getOperand(0));
1077710777
SDValue Op2 = DAG.getNode(ISD::VECTOR_REVERSE, DL, WidenVT, Op1);
10778-
return DAG.getNode(ISD::TRUNCATE, DL, VecVT, Op2);
10778+
return DAG.getSetCC(DL, VecVT, Op2,
10779+
DAG.getConstant(0, DL, Op2.getValueType()), ISD::SETNE);
1077910780
}
1078010781

1078110782
MVT ContainerVT = VecVT;

‎llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

Lines changed: 24 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,7 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
2424
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
2525
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
2626
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
27-
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
28-
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
27+
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0
2928
; RV32-BITS-UNKNOWN-NEXT: ret
3029
;
3130
; RV32-BITS-256-LABEL: reverse_nxv2i1:
@@ -39,8 +38,7 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
3938
; RV32-BITS-256-NEXT: vid.v v9
4039
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
4140
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
42-
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
43-
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
41+
; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0
4442
; RV32-BITS-256-NEXT: ret
4543
;
4644
; RV32-BITS-512-LABEL: reverse_nxv2i1:
@@ -54,8 +52,7 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
5452
; RV32-BITS-512-NEXT: vid.v v9
5553
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
5654
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
57-
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
58-
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
55+
; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0
5956
; RV32-BITS-512-NEXT: ret
6057
;
6158
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i1:
@@ -71,8 +68,7 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
7168
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
7269
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
7370
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
74-
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
75-
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
71+
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0
7672
; RV64-BITS-UNKNOWN-NEXT: ret
7773
;
7874
; RV64-BITS-256-LABEL: reverse_nxv2i1:
@@ -86,8 +82,7 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
8682
; RV64-BITS-256-NEXT: vid.v v9
8783
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
8884
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
89-
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
90-
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
85+
; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0
9186
; RV64-BITS-256-NEXT: ret
9287
;
9388
; RV64-BITS-512-LABEL: reverse_nxv2i1:
@@ -101,8 +96,7 @@ define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
10196
; RV64-BITS-512-NEXT: vid.v v9
10297
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
10398
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
104-
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
105-
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
99+
; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0
106100
; RV64-BITS-512-NEXT: ret
107101
%res = call <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1> %a)
108102
ret <vscale x 2 x i1> %res
@@ -122,8 +116,7 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
122116
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
123117
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
124118
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
125-
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
126-
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
119+
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0
127120
; RV32-BITS-UNKNOWN-NEXT: ret
128121
;
129122
; RV32-BITS-256-LABEL: reverse_nxv4i1:
@@ -137,8 +130,7 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
137130
; RV32-BITS-256-NEXT: vid.v v9
138131
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
139132
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
140-
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
141-
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
133+
; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0
142134
; RV32-BITS-256-NEXT: ret
143135
;
144136
; RV32-BITS-512-LABEL: reverse_nxv4i1:
@@ -152,8 +144,7 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
152144
; RV32-BITS-512-NEXT: vid.v v9
153145
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
154146
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
155-
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
156-
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
147+
; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0
157148
; RV32-BITS-512-NEXT: ret
158149
;
159150
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i1:
@@ -169,8 +160,7 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
169160
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
170161
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
171162
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
172-
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
173-
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
163+
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0
174164
; RV64-BITS-UNKNOWN-NEXT: ret
175165
;
176166
; RV64-BITS-256-LABEL: reverse_nxv4i1:
@@ -184,8 +174,7 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
184174
; RV64-BITS-256-NEXT: vid.v v9
185175
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
186176
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
187-
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
188-
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
177+
; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0
189178
; RV64-BITS-256-NEXT: ret
190179
;
191180
; RV64-BITS-512-LABEL: reverse_nxv4i1:
@@ -199,8 +188,7 @@ define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
199188
; RV64-BITS-512-NEXT: vid.v v9
200189
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
201190
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
202-
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
203-
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
191+
; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0
204192
; RV64-BITS-512-NEXT: ret
205193
%res = call <vscale x 4 x i1> @llvm.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)
206194
ret <vscale x 4 x i1> %res
@@ -219,8 +207,7 @@ define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
219207
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
220208
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
221209
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
222-
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1
223-
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
210+
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v9, 0
224211
; RV32-BITS-UNKNOWN-NEXT: ret
225212
;
226213
; RV32-BITS-256-LABEL: reverse_nxv8i1:
@@ -233,8 +220,7 @@ define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
233220
; RV32-BITS-256-NEXT: vid.v v9
234221
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
235222
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
236-
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
237-
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
223+
; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0
238224
; RV32-BITS-256-NEXT: ret
239225
;
240226
; RV32-BITS-512-LABEL: reverse_nxv8i1:
@@ -247,8 +233,7 @@ define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
247233
; RV32-BITS-512-NEXT: vid.v v9
248234
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
249235
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
250-
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
251-
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
236+
; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0
252237
; RV32-BITS-512-NEXT: ret
253238
;
254239
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1:
@@ -263,8 +248,7 @@ define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
263248
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
264249
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
265250
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
266-
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1
267-
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
251+
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v9, 0
268252
; RV64-BITS-UNKNOWN-NEXT: ret
269253
;
270254
; RV64-BITS-256-LABEL: reverse_nxv8i1:
@@ -277,8 +261,7 @@ define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
277261
; RV64-BITS-256-NEXT: vid.v v9
278262
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
279263
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
280-
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
281-
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
264+
; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0
282265
; RV64-BITS-256-NEXT: ret
283266
;
284267
; RV64-BITS-512-LABEL: reverse_nxv8i1:
@@ -291,8 +274,7 @@ define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
291274
; RV64-BITS-512-NEXT: vid.v v9
292275
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
293276
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
294-
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
295-
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
277+
; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0
296278
; RV64-BITS-512-NEXT: ret
297279
%res = call <vscale x 8 x i1> @llvm.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)
298280
ret <vscale x 8 x i1> %res
@@ -313,8 +295,7 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
313295
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v8
314296
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v8
315297
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma
316-
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1
317-
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
298+
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0
318299
; RV32-BITS-UNKNOWN-NEXT: ret
319300
;
320301
; RV32-BITS-256-LABEL: reverse_nxv16i1:
@@ -331,8 +312,7 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
331312
; RV32-BITS-256-NEXT: vrgather.vv v13, v10, v8
332313
; RV32-BITS-256-NEXT: vrgather.vv v12, v11, v8
333314
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
334-
; RV32-BITS-256-NEXT: vand.vi v8, v12, 1
335-
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
315+
; RV32-BITS-256-NEXT: vmsne.vi v0, v12, 0
336316
; RV32-BITS-256-NEXT: ret
337317
;
338318
; RV32-BITS-512-LABEL: reverse_nxv16i1:
@@ -349,8 +329,7 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
349329
; RV32-BITS-512-NEXT: vrgather.vv v13, v10, v8
350330
; RV32-BITS-512-NEXT: vrgather.vv v12, v11, v8
351331
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
352-
; RV32-BITS-512-NEXT: vand.vi v8, v12, 1
353-
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
332+
; RV32-BITS-512-NEXT: vmsne.vi v0, v12, 0
354333
; RV32-BITS-512-NEXT: ret
355334
;
356335
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i1:
@@ -367,8 +346,7 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
367346
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v8
368347
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v8
369348
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma
370-
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1
371-
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
349+
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0
372350
; RV64-BITS-UNKNOWN-NEXT: ret
373351
;
374352
; RV64-BITS-256-LABEL: reverse_nxv16i1:
@@ -385,8 +363,7 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
385363
; RV64-BITS-256-NEXT: vrgather.vv v13, v10, v8
386364
; RV64-BITS-256-NEXT: vrgather.vv v12, v11, v8
387365
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
388-
; RV64-BITS-256-NEXT: vand.vi v8, v12, 1
389-
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
366+
; RV64-BITS-256-NEXT: vmsne.vi v0, v12, 0
390367
; RV64-BITS-256-NEXT: ret
391368
;
392369
; RV64-BITS-512-LABEL: reverse_nxv16i1:
@@ -403,8 +380,7 @@ define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
403380
; RV64-BITS-512-NEXT: vrgather.vv v13, v10, v8
404381
; RV64-BITS-512-NEXT: vrgather.vv v12, v11, v8
405382
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
406-
; RV64-BITS-512-NEXT: vand.vi v8, v12, 1
407-
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
383+
; RV64-BITS-512-NEXT: vmsne.vi v0, v12, 0
408384
; RV64-BITS-512-NEXT: ret
409385
%res = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %a)
410386
ret <vscale x 16 x i1> %res
@@ -427,7 +403,6 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
427403
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v18, v12
428404
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v19, v12
429405
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
430-
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
431406
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
432407
; RV32-BITS-UNKNOWN-NEXT: ret
433408
;
@@ -447,7 +422,6 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
447422
; RV32-BITS-256-NEXT: vrgather.vv v9, v18, v12
448423
; RV32-BITS-256-NEXT: vrgather.vv v8, v19, v12
449424
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
450-
; RV32-BITS-256-NEXT: vand.vi v8, v8, 1
451425
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
452426
; RV32-BITS-256-NEXT: ret
453427
;
@@ -467,7 +441,6 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
467441
; RV32-BITS-512-NEXT: vrgather.vv v9, v18, v12
468442
; RV32-BITS-512-NEXT: vrgather.vv v8, v19, v12
469443
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
470-
; RV32-BITS-512-NEXT: vand.vi v8, v8, 1
471444
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
472445
; RV32-BITS-512-NEXT: ret
473446
;
@@ -487,7 +460,6 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
487460
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v18, v12
488461
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v19, v12
489462
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
490-
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
491463
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
492464
; RV64-BITS-UNKNOWN-NEXT: ret
493465
;
@@ -507,7 +479,6 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
507479
; RV64-BITS-256-NEXT: vrgather.vv v9, v18, v12
508480
; RV64-BITS-256-NEXT: vrgather.vv v8, v19, v12
509481
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
510-
; RV64-BITS-256-NEXT: vand.vi v8, v8, 1
511482
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
512483
; RV64-BITS-256-NEXT: ret
513484
;
@@ -527,7 +498,6 @@ define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
527498
; RV64-BITS-512-NEXT: vrgather.vv v9, v18, v12
528499
; RV64-BITS-512-NEXT: vrgather.vv v8, v19, v12
529500
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
530-
; RV64-BITS-512-NEXT: vand.vi v8, v8, 1
531501
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
532502
; RV64-BITS-512-NEXT: ret
533503
%res = call <vscale x 32 x i1> @llvm.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)
@@ -555,7 +525,6 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
555525
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v30, v16
556526
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v31, v16
557527
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
558-
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
559528
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
560529
; RV32-BITS-UNKNOWN-NEXT: ret
561530
;
@@ -579,7 +548,6 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
579548
; RV32-BITS-256-NEXT: vrgather.vv v9, v22, v24
580549
; RV32-BITS-256-NEXT: vrgather.vv v8, v23, v24
581550
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
582-
; RV32-BITS-256-NEXT: vand.vi v8, v8, 1
583551
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
584552
; RV32-BITS-256-NEXT: ret
585553
;
@@ -603,7 +571,6 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
603571
; RV32-BITS-512-NEXT: vrgather.vv v9, v22, v24
604572
; RV32-BITS-512-NEXT: vrgather.vv v8, v23, v24
605573
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
606-
; RV32-BITS-512-NEXT: vand.vi v8, v8, 1
607574
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
608575
; RV32-BITS-512-NEXT: ret
609576
;
@@ -627,7 +594,6 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
627594
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v30, v16
628595
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v31, v16
629596
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
630-
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v8, 1
631597
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
632598
; RV64-BITS-UNKNOWN-NEXT: ret
633599
;
@@ -651,7 +617,6 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
651617
; RV64-BITS-256-NEXT: vrgather.vv v9, v22, v24
652618
; RV64-BITS-256-NEXT: vrgather.vv v8, v23, v24
653619
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
654-
; RV64-BITS-256-NEXT: vand.vi v8, v8, 1
655620
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
656621
; RV64-BITS-256-NEXT: ret
657622
;
@@ -675,7 +640,6 @@ define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
675640
; RV64-BITS-512-NEXT: vrgather.vv v9, v22, v24
676641
; RV64-BITS-512-NEXT: vrgather.vv v8, v23, v24
677642
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
678-
; RV64-BITS-512-NEXT: vand.vi v8, v8, 1
679643
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
680644
; RV64-BITS-512-NEXT: ret
681645
%res = call <vscale x 64 x i1> @llvm.vector.reverse.nxv64i1(<vscale x 64 x i1> %a)

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