Skip to content

Commit 8e9e4f8

Browse files
rampitecrampitec
authored
[AMDGPU] Remove VT helpers isFloatType, isPackedType, simplify isIntType (#77987)
1 parent c4c53ae commit 8e9e4f8

File tree

7 files changed

+43
-107
lines changed

7 files changed

+43
-107
lines changed

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -780,9 +780,8 @@ class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
780780

781781
multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
782782
RegisterClass vdataClass,
783-
ValueType vdataType,
784-
bit isFP = isFloatType<vdataType>.ret> {
785-
let FPAtomic = isFP in {
783+
ValueType vdataType> {
784+
let FPAtomic = vdataType.isFP in {
786785
def _OFFSET : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass, 0>,
787786
MUBUFAddr64Table <0, NAME>;
788787
def _ADDR64 : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, 0>,
@@ -804,9 +803,8 @@ multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
804803
multiclass MUBUF_Pseudo_Atomics_RTN <string opName,
805804
RegisterClass vdataClass,
806805
ValueType vdataType,
807-
SDPatternOperator atomic,
808-
bit isFP = isFloatType<vdataType>.ret> {
809-
let FPAtomic = isFP in {
806+
SDPatternOperator atomic> {
807+
let FPAtomic = vdataType.isFP in {
810808
def _OFFSET_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass, 0,
811809
[(set vdataType:$vdata,
812810
(atomic (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset),

‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 8 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,6 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN<
535535
ValueType vt,
536536
ValueType data_vt = vt,
537537
RegisterClass data_rc = vdst_rc,
538-
bit isFP = isFloatType<data_vt>.ret,
539538
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
540539
def "" : FLAT_AtomicNoRet_Pseudo <opName,
541540
(outs),
@@ -544,7 +543,7 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN<
544543
GlobalSaddrTable<0, opName>,
545544
AtomicNoRet <opName, 0> {
546545
let PseudoInstr = NAME;
547-
let FPAtomic = isFP;
546+
let FPAtomic = data_vt.isFP;
548547
let AddedComplexity = -1; // Prefer global atomics if available
549548
}
550549
}
@@ -555,15 +554,14 @@ multiclass FLAT_Atomic_Pseudo_RTN<
555554
ValueType vt,
556555
ValueType data_vt = vt,
557556
RegisterClass data_rc = vdst_rc,
558-
bit isFP = isFloatType<data_vt>.ret,
559557
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
560558
def _RTN : FLAT_AtomicRet_Pseudo <opName,
561559
(outs getLdStRegisterOperand<vdst_rc>.ret:$vdst),
562560
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_GLC1:$cpol),
563561
" $vdst, $vaddr, $vdata$offset$cpol">,
564562
GlobalSaddrTable<0, opName#"_rtn">,
565563
AtomicNoRet <opName, 1> {
566-
let FPAtomic = isFP;
564+
let FPAtomic = data_vt.isFP;
567565
let AddedComplexity = -1; // Prefer global atomics if available
568566
}
569567
}
@@ -574,10 +572,9 @@ multiclass FLAT_Atomic_Pseudo<
574572
ValueType vt,
575573
ValueType data_vt = vt,
576574
RegisterClass data_rc = vdst_rc,
577-
bit isFP = isFloatType<data_vt>.ret,
578575
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
579-
defm "" : FLAT_Atomic_Pseudo_NO_RTN<opName, vdst_rc, vt, data_vt, data_rc, isFP, data_op>;
580-
defm "" : FLAT_Atomic_Pseudo_RTN<opName, vdst_rc, vt, data_vt, data_rc, isFP, data_op>;
576+
defm "" : FLAT_Atomic_Pseudo_NO_RTN<opName, vdst_rc, vt, data_vt, data_rc, data_op>;
577+
defm "" : FLAT_Atomic_Pseudo_RTN<opName, vdst_rc, vt, data_vt, data_rc, data_op>;
581578
}
582579

583580
multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
@@ -586,7 +583,6 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
586583
ValueType vt,
587584
ValueType data_vt = vt,
588585
RegisterClass data_rc = vdst_rc,
589-
bit isFP = isFloatType<data_vt>.ret,
590586
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret> {
591587

592588
def "" : FLAT_AtomicNoRet_Pseudo <opName,
@@ -597,7 +593,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
597593
AtomicNoRet <opName, 0> {
598594
let has_saddr = 1;
599595
let PseudoInstr = NAME;
600-
let FPAtomic = isFP;
596+
let FPAtomic = data_vt.isFP;
601597
}
602598

603599
def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
@@ -609,7 +605,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
609605
let has_saddr = 1;
610606
let enabled_saddr = 1;
611607
let PseudoInstr = NAME#"_SADDR";
612-
let FPAtomic = isFP;
608+
let FPAtomic = data_vt.isFP;
613609
}
614610
}
615611

@@ -619,7 +615,6 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
619615
ValueType vt,
620616
ValueType data_vt = vt,
621617
RegisterClass data_rc = vdst_rc,
622-
bit isFP = isFloatType<data_vt>.ret,
623618
RegisterOperand data_op = getLdStRegisterOperand<data_rc>.ret,
624619
RegisterOperand vdst_op = getLdStRegisterOperand<vdst_rc>.ret> {
625620

@@ -630,7 +625,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
630625
GlobalSaddrTable<0, opName#"_rtn">,
631626
AtomicNoRet <opName, 1> {
632627
let has_saddr = 1;
633-
let FPAtomic = isFP;
628+
let FPAtomic = data_vt.isFP;
634629
}
635630

636631
def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
@@ -642,7 +637,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
642637
let has_saddr = 1;
643638
let enabled_saddr = 1;
644639
let PseudoInstr = NAME#"_SADDR_RTN";
645-
let FPAtomic = isFP;
640+
let FPAtomic = data_vt.isFP;
646641
}
647642
}
648643

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 23 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -281,56 +281,10 @@ def SIfptrunc_round_downward : SDNode<"AMDGPUISD::FPTRUNC_ROUND_DOWNWARD",
281281
// ValueType helpers
282282
//===----------------------------------------------------------------------===//
283283

284-
// Returns 1 if the source arguments have modifiers, 0 if they do not.
285-
class isFloatType<ValueType SrcVT> {
286-
bit ret = !or(!eq(SrcVT.Value, f16.Value),
287-
!eq(SrcVT.Value, bf16.Value),
288-
!eq(SrcVT.Value, f32.Value),
289-
!eq(SrcVT.Value, f64.Value),
290-
!eq(SrcVT.Value, v2f16.Value),
291-
!eq(SrcVT.Value, v2bf16.Value),
292-
!eq(SrcVT.Value, v4f16.Value),
293-
!eq(SrcVT.Value, v4bf16.Value),
294-
!eq(SrcVT.Value, v8f16.Value),
295-
!eq(SrcVT.Value, v8bf16.Value),
296-
!eq(SrcVT.Value, v16f16.Value),
297-
!eq(SrcVT.Value, v16bf16.Value),
298-
!eq(SrcVT.Value, v2f32.Value),
299-
!eq(SrcVT.Value, v4f32.Value),
300-
!eq(SrcVT.Value, v8f32.Value),
301-
!eq(SrcVT.Value, v2f64.Value),
302-
!eq(SrcVT.Value, v4f64.Value));
303-
}
304-
305-
// XXX - do v2i16 instructions?
306284
class isIntType<ValueType SrcVT> {
307-
bit ret = !or(!eq(SrcVT.Value, i8.Value),
308-
!eq(SrcVT.Value, i16.Value),
309-
!eq(SrcVT.Value, i32.Value),
310-
!eq(SrcVT.Value, i64.Value),
311-
!eq(SrcVT.Value, v4i16.Value),
312-
!eq(SrcVT.Value, v8i16.Value),
313-
!eq(SrcVT.Value, v16i16.Value),
314-
!eq(SrcVT.Value, v2i32.Value),
315-
!eq(SrcVT.Value, v4i32.Value),
316-
!eq(SrcVT.Value, v8i32.Value));
285+
bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value));
317286
}
318287

319-
class isPackedType<ValueType SrcVT> {
320-
bit ret = !or(!eq(SrcVT.Value, v2i16.Value),
321-
!eq(SrcVT.Value, v2f16.Value),
322-
!eq(SrcVT.Value, v2bf16.Value),
323-
!eq(SrcVT.Value, v4f16.Value),
324-
!eq(SrcVT.Value, v4bf16.Value),
325-
!eq(SrcVT.Value, v2i32.Value),
326-
!eq(SrcVT.Value, v2f32.Value),
327-
!eq(SrcVT.Value, v4i32.Value),
328-
!eq(SrcVT.Value, v4f32.Value),
329-
!eq(SrcVT.Value, v8i32.Value),
330-
!eq(SrcVT.Value, v8f32.Value));
331-
}
332-
333-
334288
//===----------------------------------------------------------------------===//
335289
// PatFrags for global memory operations
336290
//===----------------------------------------------------------------------===//
@@ -1003,7 +957,7 @@ def ExpSrc3 : RegisterOperand<VGPR_32> {
1003957

1004958
class SDWASrc<ValueType vt> : RegisterOperand<VS_32> {
1005959
let OperandNamespace = "AMDGPU";
1006-
string Type = !if(isFloatType<vt>.ret, "FP", "INT");
960+
string Type = !if(vt.isFP, "FP", "INT");
1007961
let OperandType = "OPERAND_REG_INLINE_C_"#Type#vt.Size;
1008962
let DecoderMethod = "decodeSDWASrc"#vt.Size;
1009963
let EncoderMethod = "getSDWASrcEncoding";
@@ -1499,10 +1453,8 @@ class getSDWADstForVT<ValueType VT> {
14991453
// Returns the register class to use for source 0 of VOP[12C]
15001454
// instructions for the given VT.
15011455
class getVOPSrc0ForVT<ValueType VT, bit IsTrue16, bit IsFake16 = 1> {
1502-
bit isFP = isFloatType<VT>.ret;
1503-
15041456
RegisterOperand ret =
1505-
!if(isFP,
1457+
!if(VT.isFP,
15061458
!if(!eq(VT.Size, 64),
15071459
VSrc_f64,
15081460
!if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
@@ -1562,21 +1514,19 @@ class getVregSrcForVT_t16<ValueType VT, bit IsFake16 = 1> {
15621514
}
15631515

15641516
class getSDWASrcForVT <ValueType VT> {
1565-
bit isFP = isFloatType<VT>.ret;
15661517
RegisterOperand retFlt = !if(!eq(VT.Size, 16), SDWASrc_f16, SDWASrc_f32);
15671518
RegisterOperand retInt = !if(!eq(VT.Size, 16), SDWASrc_i16, SDWASrc_i32);
1568-
RegisterOperand ret = !if(isFP, retFlt, retInt);
1519+
RegisterOperand ret = !if(VT.isFP, retFlt, retInt);
15691520
}
15701521

15711522
// Returns the register class to use for sources of VOP3 instructions for the
15721523
// given VT.
15731524
class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
1574-
bit isFP = isFloatType<VT>.ret;
15751525
RegisterOperand ret =
15761526
!if(!eq(VT.Size, 128),
15771527
VRegSrc_128,
15781528
!if(!eq(VT.Size, 64),
1579-
!if(isFP,
1529+
!if(VT.isFP,
15801530
!if(!eq(VT.Value, v2f32.Value),
15811531
VSrc_v2f32,
15821532
VSrc_f64),
@@ -1585,7 +1535,7 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
15851535
VSrc_b64)),
15861536
!if(!eq(VT.Value, i1.Value),
15871537
SSrc_i1,
1588-
!if(isFP,
1538+
!if(VT.isFP,
15891539
!if(!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
15901540
!if(IsTrue16, VSrcT_f16, VSrc_f16),
15911541
!if(!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)),
@@ -1611,10 +1561,9 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
16111561

16121562
// Src2 of VOP3 DPP instructions cannot be a literal
16131563
class getVOP3DPPSrcForVT<ValueType VT> {
1614-
bit isFP = isFloatType<VT>.ret;
16151564
RegisterOperand ret =
16161565
!if (!eq(VT.Value, i1.Value), SSrc_i1,
1617-
!if (isFP,
1566+
!if (VT.isFP,
16181567
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), VCSrc_f16,
16191568
!if (!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)), VCSrc_v2f16, VCSrc_f32)),
16201569
!if (!eq(VT.Value, i16.Value), VCSrc_b16,
@@ -1650,14 +1599,12 @@ class isModifierType<ValueType SrcVT> {
16501599

16511600
// Return type of input modifiers operand for specified input operand
16521601
class getSrcMod <ValueType VT, bit IsTrue16 = 0> {
1653-
bit isFP = isFloatType<VT>.ret;
1654-
bit isPacked = isPackedType<VT>.ret;
16551602
Operand ret = !if(!eq(VT.Size, 64),
1656-
!if(isFP, FP64InputMods, Int64InputMods),
1603+
!if(VT.isFP, FP64InputMods, Int64InputMods),
16571604
!if(!eq(VT.Size, 16),
1658-
!if(isFP, !if(IsTrue16, FPT16InputMods, FP16InputMods),
1659-
!if(IsTrue16, IntT16InputMods, IntOpSelMods)),
1660-
!if(isFP, FP32InputMods, Int32InputMods)));
1605+
!if(VT.isFP, !if(IsTrue16, FPT16InputMods, FP16InputMods),
1606+
!if(IsTrue16, IntT16InputMods, IntOpSelMods)),
1607+
!if(VT.isFP, FP32InputMods, Int32InputMods)));
16611608
}
16621609

16631610
class getOpSelMod <ValueType VT> {
@@ -1667,14 +1614,12 @@ class getOpSelMod <ValueType VT> {
16671614

16681615
// Return type of input modifiers operand specified input operand for DPP
16691616
class getSrcModDPP <ValueType VT> {
1670-
bit isFP = isFloatType<VT>.ret;
1671-
Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
1617+
Operand ret = !if(VT.isFP, FPVRegInputMods, IntVRegInputMods);
16721618
}
16731619

16741620
class getSrcModDPP_t16 <ValueType VT> {
1675-
bit isFP = isFloatType<VT>.ret;
16761621
Operand ret =
1677-
!if (isFP,
1622+
!if (VT.isFP,
16781623
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
16791624
FPT16VRegInputMods, FPVRegInputMods),
16801625
!if (!eq(VT.Value, i16.Value), IntT16VRegInputMods,
@@ -1683,10 +1628,8 @@ class getSrcModDPP_t16 <ValueType VT> {
16831628

16841629
// Return type of input modifiers operand for specified input operand for DPP
16851630
class getSrcModVOP3DPP <ValueType VT> {
1686-
bit isFP = isFloatType<VT>.ret;
1687-
bit isPacked = isPackedType<VT>.ret;
16881631
Operand ret =
1689-
!if (isFP,
1632+
!if (VT.isFP,
16901633
!if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)),
16911634
FP16VCSrcInputMods, FP32VCSrcInputMods),
16921635
Int32VCSrcInputMods);
@@ -2330,26 +2273,26 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
23302273
field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value);
23312274
field bit HasSrc2 = !ne(Src2VT.Value, untyped.Value);
23322275

2333-
field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
2334-
field bit HasSrc1FloatMods = isFloatType<Src1VT>.ret;
2335-
field bit HasSrc2FloatMods = isFloatType<Src2VT>.ret;
2276+
field bit HasSrc0FloatMods = Src0VT.isFP;
2277+
field bit HasSrc1FloatMods = Src1VT.isFP;
2278+
field bit HasSrc2FloatMods = Src2VT.isFP;
23362279

23372280
field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
23382281
field bit HasSrc1IntMods = isIntType<Src1VT>.ret;
23392282
field bit HasSrc2IntMods = isIntType<Src2VT>.ret;
23402283

23412284
field bit HasClamp = !or(isModifierType<Src0VT>.ret, EnableClamp);
23422285
field bit HasSDWAClamp = EmitDst;
2343-
field bit HasFPClamp = !and(isFloatType<DstVT>.ret, HasClamp);
2344-
field bit HasIntClamp = !if(isFloatType<DstVT>.ret, 0, HasClamp);
2286+
field bit HasFPClamp = !and(DstVT.isFP, HasClamp);
2287+
field bit HasIntClamp = !if(DstVT.isFP, 0, HasClamp);
23452288
field bit HasClampLo = HasClamp;
2346-
field bit HasClampHi = !and(isPackedType<DstVT>.ret, HasClamp);
2289+
field bit HasClampHi = !and(DstVT.isVector, HasClamp);
23472290
field bit HasHigh = 0;
23482291

2349-
field bit IsPacked = isPackedType<Src0VT>.ret;
2292+
field bit IsPacked = Src0VT.isVector;
23502293
field bit HasOpSel = IsPacked;
2351-
field bit HasOMod = !if(IsVOP3P, 0, isFloatType<DstVT>.ret);
2352-
field bit HasSDWAOMod = isFloatType<DstVT>.ret;
2294+
field bit HasOMod = !if(IsVOP3P, 0, DstVT.isFP);
2295+
field bit HasSDWAOMod = DstVT.isFP;
23532296

23542297
field bit HasModifiers = !or(isModifierType<Src0VT>.ret,
23552298
isModifierType<Src1VT>.ret,

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1On
4848
let mayStore = 0;
4949
let hasSideEffects = 0;
5050

51-
let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
51+
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
5252

5353
let mayRaiseFPException = ReadsModeReg;
5454

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suf
6969
let mayStore = 0;
7070
let hasSideEffects = 0;
7171

72-
let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
72+
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
7373

7474
let mayRaiseFPException = ReadsModeReg;
7575

‎llvm/lib/Target/AMDGPU/VOPCInstructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -108,8 +108,8 @@ class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0,
108108
let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
109109
Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
110110
src0_sel:$src0_sel, src1_sel:$src1_sel);
111-
let AsmVOP3Base = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
112-
"$src0, $src1");
111+
let AsmVOP3Base = !if(Src0VT.isFP, "$src0_modifiers, $src1_modifiers$clamp",
112+
"$src0, $src1");
113113
let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
114114
let EmitDst = 0;
115115
}
@@ -146,7 +146,7 @@ class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
146146
let mayStore = 0;
147147
let hasSideEffects = 0;
148148

149-
let ReadsModeReg = isFloatType<P.Src0VT>.ret;
149+
let ReadsModeReg = P.Src0VT.isFP;
150150

151151
let VALU = 1;
152152
let VOPC = 1;

‎llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
152152
let ClampLo = P.HasClampLo;
153153
let ClampHi = P.HasClampHi;
154154

155-
let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
155+
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
156156

157157
let mayRaiseFPException = ReadsModeReg;
158158
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
@@ -599,7 +599,7 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
599599
let VALU = 1;
600600
let SDWA = 1;
601601

602-
let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
602+
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
603603

604604
let mayRaiseFPException = ReadsModeReg;
605605
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
@@ -811,7 +811,7 @@ class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[],
811811
let DPP = 1;
812812
let Size = 8;
813813

814-
let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
814+
let ReadsModeReg = !or(P.DstVT.isFP, P.Src0VT.isFP);
815815

816816
let mayRaiseFPException = ReadsModeReg;
817817
let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);

0 commit comments

Comments
 (0)