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Revert "[ADT] Fix specialization of ValueIsPresent for PointerUnion (#121847)"
This reverts commit 7b05367.
1 parent 8a1174f commit 8f22647

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4 files changed

+8
-13
lines changed

4 files changed

+8
-13
lines changed

llvm/include/llvm/Support/Casting.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -614,12 +614,12 @@ template <typename T> struct ValueIsPresent<std::optional<T>> {
614614
static inline decltype(auto) unwrapValue(std::optional<T> &t) { return *t; }
615615
};
616616

617-
// If something is "nullable" then we just cast it to bool to see if it exists.
617+
// If something is "nullable" then we just compare it to nullptr to see if it
618+
// exists.
618619
template <typename T>
619-
struct ValueIsPresent<
620-
T, std::enable_if_t<IsNullable<T> && std::is_constructible_v<bool, T>>> {
620+
struct ValueIsPresent<T, std::enable_if_t<IsNullable<T>>> {
621621
using UnwrappedType = T;
622-
static inline bool isPresent(const T &t) { return static_cast<bool>(t); }
622+
static inline bool isPresent(const T &t) { return t != T(nullptr); }
623623
static inline decltype(auto) unwrapValue(T &t) { return t; }
624624
};
625625

llvm/lib/CodeGen/RegisterBankInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -134,10 +134,10 @@ const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
134134

135135
// If the register already has a class, fallback to MRI::constrainRegClass.
136136
auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
137-
if (isa_and_present<const TargetRegisterClass *>(RegClassOrBank))
137+
if (isa<const TargetRegisterClass *>(RegClassOrBank))
138138
return MRI.constrainRegClass(Reg, &RC);
139139

140-
const auto *RB = dyn_cast_if_present<const RegisterBank *>(RegClassOrBank);
140+
const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank);
141141
// Otherwise, all we can do is ensure the bank covers the class, and set it.
142142
if (RB && !RB->covers(RC))
143143
return nullptr;

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3708,10 +3708,10 @@ const TargetRegisterClass *
37083708
SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
37093709
const MachineRegisterInfo &MRI) const {
37103710
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
3711-
if (const auto *RB = dyn_cast_if_present<const RegisterBank *>(RCOrRB))
3711+
if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(RCOrRB))
37123712
return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB);
37133713

3714-
if (const auto *RC = dyn_cast_if_present<const TargetRegisterClass *>(RCOrRB))
3714+
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RCOrRB))
37153715
return getAllocatableClass(RC);
37163716

37173717
return nullptr;

llvm/unittests/ADT/PointerUnionTest.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -208,11 +208,6 @@ TEST_F(PointerUnionTest, NewCastInfra) {
208208
EXPECT_FALSE(isa<float *>(d4null));
209209
EXPECT_FALSE(isa<long long *>(d4null));
210210

211-
EXPECT_FALSE(isa_and_present<int *>(i4null));
212-
EXPECT_FALSE(isa_and_present<float *>(f4null));
213-
EXPECT_FALSE(isa_and_present<long long *>(l4null));
214-
EXPECT_FALSE(isa_and_present<double *>(d4null));
215-
216211
// test cast<>
217212
EXPECT_EQ(cast<float *>(a), &f);
218213
EXPECT_EQ(cast<int *>(b), &i);

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