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add support for encoding the lo14 forms used for a few PPC64 addressing
modes. For example, we now get: ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00] ; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14 llvm-svn: 119133
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5 files changed

+45
-25
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5 files changed

+45
-25
lines changed

‎llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ namespace {
6666

6767
unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
6868
unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
69-
unsigned getLO14Encoding(const MachineInstr &MI, unsigned OpNo) const;
69+
unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
7070

7171
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
7272

@@ -209,13 +209,19 @@ unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI,
209209
return 0;
210210
}
211211

212-
unsigned PPCCodeEmitter::getLO14Encoding(const MachineInstr &MI,
213-
unsigned OpNo) const {
212+
unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
213+
unsigned OpNo) const {
214+
// Encode (imm, reg) as a memrix, which has the low 14-bits as the
215+
// displacement and the next 5 bits as the register #.
216+
assert(MI.getOperand(OpNo+1).isReg());
217+
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
218+
214219
const MachineOperand &MO = MI.getOperand(OpNo);
215-
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
220+
if (MO.isImm())
221+
return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits;
216222

217223
MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
218-
return 0;
224+
return RegBits;
219225
}
220226

221227

@@ -259,13 +265,6 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
259265
case PPC::STFD:
260266
Reloc = PPC::reloc_absolute_low;
261267
break;
262-
263-
case PPC::LWA:
264-
case PPC::LD:
265-
case PPC::STD:
266-
case PPC::STD_32:
267-
Reloc = PPC::reloc_absolute_low_ix;
268-
break;
269268
}
270269

271270
MCE.addRelocation(GetRelocation(MO, Reloc));

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -552,12 +552,13 @@ def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
552552
"",
553553
[(set G8RC:$rD,
554554
(PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
555-
let RST = 2, DS = 8 in
555+
556+
let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
556557
def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg),
557558
"ld 2, 8($reg)", LdStLD,
558559
[(PPCload_toc G8RC:$reg)]>, isPPC64;
559560

560-
let RST = 2, DS = 40, RA = 1 in
561+
let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
561562
def LDtoc_restore : DSForm_1<58, 0, (outs), (ins),
562563
"ld 2, 40(1)", LdStLD,
563564
[(PPCtoc_restore)]>, isPPC64;
@@ -628,8 +629,8 @@ def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
628629
iaddroff:$ptroff))]>,
629630
RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
630631

631-
def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
632-
s16immX4:$ptroff, ptr_rc:$ptrreg),
632+
def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
633+
s16immX4:$ptroff, ptr_rc:$ptrreg),
633634
"stdu $rS, $ptroff($ptrreg)", LdStSTD,
634635
[(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
635636
iaddroff:$ptroff))]>,

‎llvm/lib/Target/PowerPC/PPCInstrFormats.td

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -188,17 +188,31 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
188188
InstrItinClass itin, list<dag> pattern>
189189
: I<opcode, OOL, IOL, asmstr, itin> {
190190
bits<5> RST;
191-
bits<14> DS;
192-
bits<5> RA;
191+
bits<19> DS_RA;
193192

194193
let Pattern = pattern;
195194

196195
let Inst{6-10} = RST;
197-
let Inst{11-15} = RA;
198-
let Inst{16-29} = DS;
196+
let Inst{11-15} = DS_RA{18-14}; // Register #
197+
let Inst{16-29} = DS_RA{13-0}; // Displacement.
199198
let Inst{30-31} = xo;
200199
}
201200

201+
class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
202+
InstrItinClass itin, list<dag> pattern>
203+
: I<opcode, OOL, IOL, asmstr, itin> {
204+
bits<5> RST;
205+
bits<14> DS;
206+
bits<5> RA;
207+
208+
let Pattern = pattern;
209+
210+
let Inst{6-10} = RST;
211+
let Inst{11-15} = RA;
212+
let Inst{16-29} = DS;
213+
let Inst{30-31} = xo;
214+
}
215+
202216
// 1.7.6 X-Form
203217
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
204218
InstrItinClass itin, list<dag> pattern>

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,7 @@ def memrr : Operand<iPTR> {
324324
def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
325325
let PrintMethod = "printMemRegImmShifted";
326326
let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
327+
let EncoderMethod = "getMemRIXEncoding";
327328
}
328329
def tocentry : Operand<iPTR> {
329330
let MIOperandInfo = (ops i32imm:$imm);

‎llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -66,8 +66,8 @@ class PPCMCCodeEmitter : public MCCodeEmitter {
6666
SmallVectorImpl<MCFixup> &Fixups) const;
6767
unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
6868
SmallVectorImpl<MCFixup> &Fixups) const;
69-
unsigned getLO14Encoding(const MCInst &MI, unsigned OpNo,
70-
SmallVectorImpl<MCFixup> &Fixups) const;
69+
unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
70+
SmallVectorImpl<MCFixup> &Fixups) const;
7171
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
7272
SmallVectorImpl<MCFixup> &Fixups) const;
7373

@@ -147,15 +147,20 @@ unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
147147
return 0;
148148
}
149149

150-
unsigned PPCMCCodeEmitter::getLO14Encoding(const MCInst &MI, unsigned OpNo,
150+
unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
151151
SmallVectorImpl<MCFixup> &Fixups) const {
152+
// Encode (imm, reg) as a memrix, which has the low 14-bits as the
153+
// displacement and the next 5 bits as the register #.
154+
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
155+
152156
const MCOperand &MO = MI.getOperand(OpNo);
153-
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
157+
if (MO.isImm())
158+
return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
154159

155160
// Add a fixup for the branch target.
156161
Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
157162
(MCFixupKind)PPC::fixup_ppc_lo14));
158-
return 0;
163+
return RegBits;
159164
}
160165

161166

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