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[LLVM][AArch64] Add assembly/disassembly for SVE Integer Unary Arithmetic Predicated instructions
This patch adds the following instructions: SVE bitwise unary operations (predicated) CLS, CLZ, CNT, CNOT, FABS, FNEG, NOT SVE integer unary operations (predicated) SXT{B,H,W}, UXT{B,H,W}, ABS ,NEG SVE2 integer unary operations (predicated) URECPE, URSQRTE, SQABS, SQNEG According to https://developer.arm.com/documentation/ddi0602 Co-authored-by: Spencer Abson [email protected]
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 47 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -647,22 +647,22 @@ let Predicates = [HasSVEorSME] in {
647647
defm SDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b0, "sdot", int_aarch64_sve_sdot_lane>;
648648
defm UDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b1, "udot", int_aarch64_sve_udot_lane>;
649649

650-
defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb", AArch64sxt_mt>;
651-
defm UXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b001, "uxtb", AArch64uxt_mt>;
652-
defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth", AArch64sxt_mt>;
653-
defm UXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b011, "uxth", AArch64uxt_mt>;
654-
defm SXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b100, "sxtw", AArch64sxt_mt>;
655-
defm UXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b101, "uxtw", AArch64uxt_mt>;
656-
defm ABS_ZPmZ : sve_int_un_pred_arit_0< 0b110, "abs", AArch64abs_mt>;
657-
defm NEG_ZPmZ : sve_int_un_pred_arit_0< 0b111, "neg", AArch64neg_mt>;
658-
659-
defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls", AArch64cls_mt>;
660-
defm CLZ_ZPmZ : sve_int_un_pred_arit_1< 0b001, "clz", AArch64clz_mt>;
661-
defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt", AArch64cnt_mt>;
662-
defm CNOT_ZPmZ : sve_int_un_pred_arit_1< 0b011, "cnot", AArch64cnot_mt>;
663-
defm NOT_ZPmZ : sve_int_un_pred_arit_1< 0b110, "not", AArch64not_mt>;
664-
defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs", AArch64fabs_mt>;
665-
defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg", AArch64fneg_mt>;
650+
defm SXTB_ZPmZ : sve_int_un_pred_arit_h<0b000, "sxtb", AArch64sxt_mt>;
651+
defm UXTB_ZPmZ : sve_int_un_pred_arit_h<0b001, "uxtb", AArch64uxt_mt>;
652+
defm SXTH_ZPmZ : sve_int_un_pred_arit_w<0b010, "sxth", AArch64sxt_mt>;
653+
defm UXTH_ZPmZ : sve_int_un_pred_arit_w<0b011, "uxth", AArch64uxt_mt>;
654+
defm SXTW_ZPmZ : sve_int_un_pred_arit_d<0b100, "sxtw", AArch64sxt_mt>;
655+
defm UXTW_ZPmZ : sve_int_un_pred_arit_d<0b101, "uxtw", AArch64uxt_mt>;
656+
defm ABS_ZPmZ : sve_int_un_pred_arit< 0b110, "abs", AArch64abs_mt>;
657+
defm NEG_ZPmZ : sve_int_un_pred_arit< 0b111, "neg", AArch64neg_mt>;
658+
659+
defm CLS_ZPmZ : sve_int_un_pred_arit_bitwise< 0b000, "cls", AArch64cls_mt>;
660+
defm CLZ_ZPmZ : sve_int_un_pred_arit_bitwise< 0b001, "clz", AArch64clz_mt>;
661+
defm CNT_ZPmZ : sve_int_un_pred_arit_bitwise< 0b010, "cnt", AArch64cnt_mt>;
662+
defm CNOT_ZPmZ : sve_int_un_pred_arit_bitwise< 0b011, "cnot", AArch64cnot_mt>;
663+
defm NOT_ZPmZ : sve_int_un_pred_arit_bitwise< 0b110, "not", AArch64not_mt>;
664+
defm FABS_ZPmZ : sve_int_un_pred_arit_bitwise_fp<0b100, "fabs", AArch64fabs_mt>;
665+
defm FNEG_ZPmZ : sve_int_un_pred_arit_bitwise_fp<0b101, "fneg", AArch64fneg_mt>;
666666

667667
foreach VT = [nxv2bf16, nxv4bf16, nxv8bf16] in {
668668
// No dedicated instruction, so just clear the sign bit.
@@ -3586,10 +3586,10 @@ let Predicates = [HasSVE2orSME] in {
35863586
defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp", int_aarch64_sve_uminp>;
35873587

35883588
// SVE2 integer unary operations (predicated)
3589-
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe", int_aarch64_sve_urecpe>;
3590-
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte", int_aarch64_sve_ursqrte>;
3591-
defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs", int_aarch64_sve_sqabs>;
3592-
defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg", int_aarch64_sve_sqneg>;
3589+
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b00, "urecpe", int_aarch64_sve_urecpe>;
3590+
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b01, "ursqrte", int_aarch64_sve_ursqrte>;
3591+
defm SQABS_ZPmZ : sve2_int_un_pred_arit< 0b10, "sqabs", int_aarch64_sve_sqabs>;
3592+
defm SQNEG_ZPmZ : sve2_int_un_pred_arit< 0b11, "sqneg", int_aarch64_sve_sqneg>;
35933593

35943594
// SVE2 saturating add/subtract
35953595
defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd", int_aarch64_sve_sqadd>;
@@ -4233,6 +4233,33 @@ let Predicates = [HasSVE2p2orSME2p2] in {
42334233
defm FRINT32X_ZPmZ : sve_fp_2op_p_zd_frint<0b01, "frint32x">;
42344234
defm FRINT64X_ZPmZ : sve_fp_2op_p_zd_frint<0b10, "frint64z">;
42354235
defm FRINT64Z_ZPmZ : sve_fp_2op_p_zd_frint<0b11, "frint64x">;
4236+
4237+
// SVE2p2 integer unary arithmetic (bitwise), zeroing predicate
4238+
defm CLS_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b000, "cls">;
4239+
defm CLZ_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b001, "clz">;
4240+
defm CNT_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b010, "cnt">;
4241+
defm CNOT_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b011, "cnot">;
4242+
defm NOT_ZPzZ : sve_int_un_pred_arit_bitwise_z<0b110, "not">;
4243+
4244+
// floating point
4245+
defm FABS_ZPzZ : sve_int_un_pred_arit_bitwise_fp_z<0b100, "fabs">;
4246+
defm FNEG_ZPzZ : sve_int_un_pred_arit_bitwise_fp_z<0b101, "fneg">;
4247+
4248+
def URECPE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b00, "urecpe", ZPR32>;
4249+
def URSQRTE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b01, "ursqrte", ZPR32>;
4250+
defm SQABS_ZPzZ : sve2_int_un_pred_arit_z<0b10, "sqabs">;
4251+
defm SQNEG_ZPzZ : sve2_int_un_pred_arit_z<0b11, "sqneg">;
4252+
4253+
// SVE2p2 integer unary arithmetic, zeroing predicate
4254+
defm SXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b000, "sxtb">;
4255+
defm UXTB_ZPzZ : sve_int_un_pred_arit_h_z<0b001, "uxtb">;
4256+
defm SXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b010, "sxth">;
4257+
defm UXTH_ZPzZ : sve_int_un_pred_arit_w_z<0b011, "uxth">;
4258+
defm ABS_ZPzZ : sve_int_un_pred_arit_z< 0b110, "abs">;
4259+
defm NEG_ZPzZ : sve_int_un_pred_arit_z< 0b111, "neg">;
4260+
def SXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1000, "sxtw", ZPR64>;
4261+
def UXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1010, "uxtw", ZPR64>;
4262+
42364263
} // End HasSME2p2orSVE2p2
42374264

42384265
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 106 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -3900,7 +3900,7 @@ multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm, SDPatternOperato
39003900
def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv4i32, !cast<Instruction>(NAME # _D)>;
39013901
}
39023902

3903-
class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
3903+
class sve2_int_un_pred_arit<bits<2> sz, bits<2> opc,
39043904
string asm, ZPRRegOp zprty>
39053905
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
39063906
asm, "\t$Zd, $Pg/m, $Zn",
@@ -3912,9 +3912,9 @@ class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
39123912
let Inst{31-24} = 0b01000100;
39133913
let Inst{23-22} = sz;
39143914
let Inst{21-20} = 0b00;
3915-
let Inst{19} = Q;
3916-
let Inst{18} = 0b0;
3917-
let Inst{17-16} = opc;
3915+
let Inst{19} = opc{1};
3916+
let Inst{18-17} = 0b00;
3917+
let Inst{16} = opc{0};
39183918
let Inst{15-13} = 0b101;
39193919
let Inst{12-10} = Pg;
39203920
let Inst{9-5} = Zn;
@@ -3926,9 +3926,32 @@ class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
39263926
let hasSideEffects = 0;
39273927
}
39283928

3929-
multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm,
3929+
class sve2_int_un_pred_arit_z<bits<2> sz, bits<2> opc,
3930+
string asm, ZPRRegOp zprty>
3931+
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
3932+
asm, "\t$Zd, $Pg/z, $Zn",
3933+
"",
3934+
[]>, Sched<[]> {
3935+
bits<3> Pg;
3936+
bits<5> Zd;
3937+
bits<5> Zn;
3938+
let Inst{31-24} = 0b01000100;
3939+
let Inst{23-22} = sz;
3940+
let Inst{21-20} = 0b00;
3941+
let Inst{19} = opc{1};
3942+
let Inst{18-17} = 0b01;
3943+
let Inst{16} = opc{0};
3944+
let Inst{15-13} = 0b101;
3945+
let Inst{12-10} = Pg;
3946+
let Inst{9-5} = Zn;
3947+
let Inst{4-0} = Zd;
3948+
3949+
let hasSideEffects = 0;
3950+
}
3951+
3952+
multiclass sve2_int_un_pred_arit_s<bits<2> opc, string asm,
39303953
SDPatternOperator op> {
3931-
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
3954+
def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>,
39323955
SVEPseudo2Instr<NAME # _S, 1>;
39333956

39343957
def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
@@ -3938,14 +3961,14 @@ multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm,
39383961
defm : SVE_3_Op_Undef_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4i32, !cast<Pseudo>(NAME # _S_UNDEF)>;
39393962
}
39403963

3941-
multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op> {
3942-
def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>,
3964+
multiclass sve2_int_un_pred_arit<bits<2> opc, string asm, SDPatternOperator op> {
3965+
def _B : sve2_int_un_pred_arit<0b00, opc, asm, ZPR8>,
39433966
SVEPseudo2Instr<NAME # _B, 1>;
3944-
def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>,
3967+
def _H : sve2_int_un_pred_arit<0b01, opc, asm, ZPR16>,
39453968
SVEPseudo2Instr<NAME # _H, 1>;
3946-
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
3969+
def _S : sve2_int_un_pred_arit<0b10, opc, asm, ZPR32>,
39473970
SVEPseudo2Instr<NAME # _S, 1>;
3948-
def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>,
3971+
def _D : sve2_int_un_pred_arit<0b11, opc, asm, ZPR64>,
39493972
SVEPseudo2Instr<NAME # _D, 1>;
39503973

39513974
def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
@@ -3964,6 +3987,13 @@ multiclass sve2_int_un_pred_arit<bits<3> opc, string asm, SDPatternOperator op>
39643987
defm : SVE_3_Op_Undef_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
39653988
}
39663989

3990+
multiclass sve2_int_un_pred_arit_z<bits<2> opc, string asm> {
3991+
def _B : sve2_int_un_pred_arit_z<0b00, opc, asm, ZPR8>;
3992+
def _H : sve2_int_un_pred_arit_z<0b01, opc, asm, ZPR16>;
3993+
def _S : sve2_int_un_pred_arit_z<0b10, opc, asm, ZPR32>;
3994+
def _D : sve2_int_un_pred_arit_z<0b11, opc, asm, ZPR64>;
3995+
}
3996+
39673997
//===----------------------------------------------------------------------===//
39683998
// SVE2 Widening Integer Arithmetic Group
39693999
//===----------------------------------------------------------------------===//
@@ -4593,8 +4623,30 @@ class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
45934623
let hasSideEffects = 0;
45944624
}
45954625

4596-
multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm,
4597-
SDPatternOperator op> {
4626+
class sve_int_un_pred_arit_z<bits<2> sz8_64, bits<4> opc,
4627+
string asm, ZPRRegOp zprty>
4628+
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
4629+
asm, "\t$Zd, $Pg/z, $Zn",
4630+
"",
4631+
[]>, Sched<[]> {
4632+
bits<3> Pg;
4633+
bits<5> Zd;
4634+
bits<5> Zn;
4635+
let Inst{31-24} = 0b00000100;
4636+
let Inst{23-22} = sz8_64;
4637+
let Inst{21-20} = 0b00;
4638+
let Inst{19} = opc{0};
4639+
let Inst{18-16} = opc{3-1};
4640+
let Inst{15-13} = 0b101;
4641+
let Inst{12-10} = Pg;
4642+
let Inst{9-5} = Zn;
4643+
let Inst{4-0} = Zd;
4644+
4645+
let hasSideEffects = 0;
4646+
}
4647+
4648+
multiclass sve_int_un_pred_arit<bits<3> opc, string asm,
4649+
SDPatternOperator op> {
45984650
def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>,
45994651
SVEPseudo2Instr<NAME # _B, 1>;
46004652
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>,
@@ -4620,8 +4672,15 @@ multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm,
46204672
defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
46214673
}
46224674

4623-
multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm,
4624-
SDPatternOperator op> {
4675+
multiclass sve_int_un_pred_arit_z<bits<3> opc, string asm> {
4676+
def _B : sve_int_un_pred_arit_z<0b00, { opc, 0b0 }, asm, ZPR8>;
4677+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b0 }, asm, ZPR16>;
4678+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
4679+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;
4680+
}
4681+
4682+
multiclass sve_int_un_pred_arit_h<bits<3> opc, string asm,
4683+
SDPatternOperator op> {
46254684
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>,
46264685
SVEPseudo2Instr<NAME # _H, 1>;
46274686
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>,
@@ -4642,8 +4701,14 @@ multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm,
46424701
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i8, !cast<Pseudo>(NAME # _D_UNDEF)>;
46434702
}
46444703

4645-
multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm,
4646-
SDPatternOperator op> {
4704+
multiclass sve_int_un_pred_arit_h_z<bits<3> opc, string asm> {
4705+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b0 }, asm, ZPR16>;
4706+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
4707+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;
4708+
}
4709+
4710+
multiclass sve_int_un_pred_arit_w<bits<3> opc, string asm,
4711+
SDPatternOperator op> {
46474712
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>,
46484713
SVEPseudo2Instr<NAME # _S, 1>;
46494714
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
@@ -4659,8 +4724,13 @@ multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm,
46594724
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i16, !cast<Pseudo>(NAME # _D_UNDEF)>;
46604725
}
46614726

4662-
multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm,
4663-
SDPatternOperator op> {
4727+
multiclass sve_int_un_pred_arit_w_z<bits<3> opc, string asm> {
4728+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b0 }, asm, ZPR32>;
4729+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b0 }, asm, ZPR64>;
4730+
}
4731+
4732+
multiclass sve_int_un_pred_arit_d<bits<3> opc, string asm,
4733+
SDPatternOperator op> {
46644734
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>,
46654735
SVEPseudo2Instr<NAME # _D, 1>;
46664736

@@ -4671,8 +4741,8 @@ multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm,
46714741
defm : SVE_InReg_Extend_PassthruUndef<nxv2i64, op, nxv2i1, nxv2i32, !cast<Pseudo>(NAME # _D_UNDEF)>;
46724742
}
46734743

4674-
multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm,
4675-
SDPatternOperator op> {
4744+
multiclass sve_int_un_pred_arit_bitwise<bits<3> opc, string asm,
4745+
SDPatternOperator op> {
46764746
def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>,
46774747
SVEPseudo2Instr<NAME # _B, 1>;
46784748
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>,
@@ -4698,7 +4768,15 @@ multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm,
46984768
defm : SVE_1_Op_PassthruUndef_Pat<nxv2i64, op, nxv2i1, nxv2i64, !cast<Pseudo>(NAME # _D_UNDEF)>;
46994769
}
47004770

4701-
multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm, SDPatternOperator op> {
4771+
multiclass sve_int_un_pred_arit_bitwise_z<bits<3> opc, string asm> {
4772+
def _B : sve_int_un_pred_arit_z<0b00, { opc, 0b1 }, asm, ZPR8>;
4773+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b1 }, asm, ZPR16>;
4774+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b1 }, asm, ZPR32>;
4775+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b1 }, asm, ZPR64>;
4776+
}
4777+
4778+
multiclass sve_int_un_pred_arit_bitwise_fp<bits<3> opc, string asm,
4779+
SDPatternOperator op> {
47024780
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>,
47034781
SVEPseudo2Instr<NAME # _H, 1>;
47044782
def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>,
@@ -4725,6 +4803,12 @@ multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm, SDPatternOperator
47254803
defm : SVE_1_Op_PassthruUndef_Pat<nxv2f64, op, nxv2i1, nxv2f64, !cast<Pseudo>(NAME # _D_UNDEF)>;
47264804
}
47274805

4806+
multiclass sve_int_un_pred_arit_bitwise_fp_z<bits<3> opc, string asm> {
4807+
def _H : sve_int_un_pred_arit_z<0b01, { opc, 0b1 }, asm, ZPR16>;
4808+
def _S : sve_int_un_pred_arit_z<0b10, { opc, 0b1 }, asm, ZPR32>;
4809+
def _D : sve_int_un_pred_arit_z<0b11, { opc, 0b1 }, asm, ZPR64>;
4810+
}
4811+
47284812
//===----------------------------------------------------------------------===//
47294813
// SVE Integer Wide Immediate - Unpredicated Group
47304814
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE2/sqabs-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
sqabs z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: sqabs z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/sqneg-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
sqneg z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: sqneg z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/urecpe-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
urecpe z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: urecpe z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

‎llvm/test/MC/AArch64/SVE2/ursqrte-diagnostics.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
// Invalid predicate
55

66
ursqrte z0.s, p0/z, z1.s
7-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
88
// CHECK-NEXT: ursqrte z0.s, p0/z, z1.s
99
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1010

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