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-67
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11 files changed

+72
-67
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‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,8 @@
157157
// CHECK-NEXT: xcvmac 1.0 'XCVmac' (CORE-V Multiply-Accumulate)
158158
// CHECK-NEXT: xcvmem 1.0 'XCVmem' (CORE-V Post-incrementing Load & Store)
159159
// CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU)
160+
// CHECK-NEXT: xmipscmove 1.0 'XMIPSCMove' (MIPS conditional move instruction(s) (ccmov))
161+
// CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
160162
// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)
161163
// CHECK-NEXT: xsfvcp 1.0 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)
162164
// CHECK-NEXT: xsfvfnrclipxfqf 1.0 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -671,10 +671,11 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
671671
"SiFive sf.cflush.d.l1 custom opcode table");
672672
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
673673
"SiFive sf.cease custom opcode table");
674-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorMIPSLoadStorePairs,
674+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSLSP,
675675
DecoderTableXmipslsp32,
676676
"MIPS mips.lsp custom opcode table");
677-
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorMIPSCMove, DecoderTableXmipscomve32,
677+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSCMove,
678+
DecoderTableXmipscmove32,
678679
"MIPS mips.ccmov custom opcode table");
679680
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
680681
DecoderTableXCVbitmanip32,

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
12281228
: Predicate<"Subtarget->hasVendorXCVbi()">,
12291229
AssemblerPredicate<(all_of FeatureVendorXCVbi),
12301230
"'XCVbi' (CORE-V Immediate Branching)">;
1231+
// MIPS Extensions
1232+
1233+
def FeatureVendorXMIPSCMove
1234+
: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
1235+
def HasVendorXMIPSCMove
1236+
: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
1237+
AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
1238+
"'Xmipscmove' ('mips.ccmov' instruction)">;
1239+
def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
1240+
def FeatureVendorXMIPSLSP
1241+
: RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;
1242+
def HasVendorXMIPSLSP
1243+
: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
1244+
AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
1245+
"'Xmipslsp' (load and store pair instructions)">;
12311246

12321247
// WCH / Nanjing Qinheng Microelectronics Extension(s)
12331248

@@ -1456,18 +1471,3 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
14561471
"AllowTaggedGlobals",
14571472
"true", "Use an instruction sequence for taking the address of a global "
14581473
"that allows a memory tag in the upper address bits">;
1459-
1460-
def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove",
1461-
"true", "Using CCMov",
1462-
[Feature64Bit]>;
1463-
def HasVendorMIPSCMove
1464-
: Predicate<"Subtarget->useCCMovInsn()">,
1465-
AssemblerPredicate<(all_of FeatureVendorMIPSCMove),
1466-
"'Xmipscmove' ('mips.ccmov' instruction)">;
1467-
def FeatureVendorMIPSLoadStorePairs
1468-
: SubtargetFeature<"xmipslsp", "HasMIPSLSP", "true",
1469-
"Optimize for hardware load-store bonding">;
1470-
def HasVendorMIPSLoadStorePairs
1471-
: Predicate<"Subtarget->useLoadStorePairs()">,
1472-
AssemblerPredicate<(all_of FeatureVendorMIPSLoadStorePairs),
1473-
"'Xmipslsp' (load and store pair instructions)">;

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -409,7 +409,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
409409
setOperationAction(ISD::ABS, MVT::i32, Custom);
410410
}
411411

412-
if (Subtarget.hasVendorMIPSCMove())
412+
if (Subtarget.useCCMovInsn())
413413
setOperationAction(ISD::SELECT, XLenVT, Legal);
414414
else if (!Subtarget.hasVendorXTHeadCondMov())
415415
setOperationAction(ISD::SELECT, XLenVT, Custom);

‎llvm/lib/Target/RISCV/RISCVInstrFormats.td

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -566,7 +566,8 @@ class SDPFormat<dag outs, dag ins, string opcodestr, string argstr>
566566
let Inst{19-15} = rs1;
567567
let Inst{14-12} = 0b101;
568568
let Inst{11-10} = imm7{4-3};
569-
let Inst{9-0} = 0b0000001011;
569+
let Inst{9-7} = 0b000;
570+
let Inst{6-0} = OPC_CUSTOM_0.Value;
570571
}
571572

572573
// Store word pair format.
@@ -583,7 +584,8 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
583584
let Inst{19-15} = rs1;
584585
let Inst{14-12} = 0b101;
585586
let Inst{11-9} = imm7{4-2};
586-
let Inst{8-0} = 0b010001011;
587+
let Inst{8-7} = 0b01;
588+
let Inst{6-0} = OPC_CUSTOM_0.Value;
587589
}
588590

589591
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -109,21 +109,6 @@ def uimm7_lsb00 : RISCVOp,
109109
}];
110110
}
111111

112-
// A 7-bit unsigned immediate where the least significant three bits are zero.
113-
def uimm7_lsb000 : RISCVOp,
114-
ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {
115-
let ParserMatchClass = UImmAsmOperand<7, "Lsb000">;
116-
let EncoderMethod = "getImmOpValue";
117-
let DecoderMethod = "decodeUImmOperand<7>";
118-
let OperandType = "OPERAND_UIMM7_LSB000";
119-
let MCOperandPredicate = [{
120-
int64_t Imm;
121-
if (!MCOp.evaluateAsConstantImm(Imm))
122-
return false;
123-
return isShiftedUInt<4, 3>(Imm);
124-
}];
125-
}
126-
127112
// A 8-bit unsigned immediate where the least significant two bits are zero.
128113
def uimm8_lsb00 : RISCVOp,
129114
ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {

‎llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

Lines changed: 37 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -11,18 +11,37 @@
1111
//===----------------------------------------------------------------------===//
1212

1313
//===----------------------------------------------------------------------===//
14+
// Operand definitions.
15+
//===----------------------------------------------------------------------===//
16+
17+
// A 7-bit unsigned immediate where the least significant three bits are zero.
18+
def uimm7_lsb000 : RISCVOp,
19+
ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {
20+
let ParserMatchClass = UImmAsmOperand<7, "Lsb000">;
21+
let EncoderMethod = "getImmOpValue";
22+
let DecoderMethod = "decodeUImmOperand<7>";
23+
let OperandType = "OPERAND_UIMM7_LSB000";
24+
let MCOperandPredicate = [{
25+
int64_t Imm;
26+
if (!MCOp.evaluateAsConstantImm(Imm))
27+
return false;
28+
return isShiftedUInt<4, 3>(Imm);
29+
}];
30+
}
1431

32+
//===----------------------------------------------------------------------===//
1533
// MIPS extensions
1634
//===----------------------------------------------------------------------===//
1735

18-
let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0, mayStore = 0, DecoderNamespace = "Xmipscomve" in {
36+
let Predicates = [HasVendorXMIPSCMove], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
37+
DecoderNamespace = "Xmipscmove" in {
1938
def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
2039
(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
2140
"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
2241
Sched<[]>;
2342
}
2443

25-
let Predicates = [HasVendorMIPSCMove] in {
44+
let Predicates = [UseCCMovInsn] in {
2645
def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
2746
(XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
2847
(CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
@@ -41,42 +60,36 @@ def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
4160
def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
4261
(XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
4362
(CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
44-
def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
45-
(XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
46-
(CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
47-
def : Pat<(select (XLenVT (setge (XLenVT GPR:$x), (XLenVT GPR:$y))),
48-
(XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
49-
(CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
50-
def : Pat<(select (XLenVT (setle (XLenVT GPR:$y), (XLenVT GPR:$x))),
51-
(XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
52-
(CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
5363
def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
5464
(CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
5565
}
5666

57-
let Predicates = [HasVendorMIPSLoadStorePairs], hasSideEffects = 0, DecoderNamespace = "Xmipslsp" in {
67+
let Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0,
68+
DecoderNamespace = "Xmipslsp" in {
69+
5870
def LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb00:$imm7),
5971
"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
60-
Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
61-
let mayLoad = 1;
62-
let mayStore = 0;
72+
Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
73+
let mayLoad = 1;
74+
let mayStore = 0;
6375
}
6476
def LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb000:$imm7),
6577
"mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
66-
Sched<[WriteLDD, WriteLDD, ReadMemBase]> {
67-
let mayLoad = 1;
68-
let mayStore = 0;
78+
Sched<[WriteLDD, WriteLDD, ReadMemBase]> {
79+
let mayLoad = 1;
80+
let mayStore = 0;
6981
}
7082
def SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb00:$imm7),
7183
"mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
72-
Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]> {
73-
let mayLoad = 0;
74-
let mayStore = 1;
84+
Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]> {
85+
let mayLoad = 0;
86+
let mayStore = 1;
7587
}
7688
def SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb000:$imm7),
7789
"mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
78-
Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]> {
79-
let mayLoad = 0;
80-
let mayStore = 1;
90+
Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]> {
91+
let mayLoad = 0;
92+
let mayStore = 1;
8193
}
94+
8295
}

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -117,8 +117,8 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
117117
FeatureStdExtZbb,
118118
FeatureStdExtZifencei,
119119
FeatureStdExtZicsr,
120-
FeatureVendorMIPSCMove,
121-
FeatureVendorMIPSLoadStorePairs],
120+
FeatureVendorXMIPSCMove,
121+
FeatureVendorXMIPSLSP],
122122
[TuneMIPSP8700]>;
123123

124124
def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -63,9 +63,9 @@ static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
6363
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
6464

6565
static cl::opt<bool>
66-
UseLoadStorePairsOpt("riscv-load-store-pairs",
67-
cl::desc("RISCV: Optimize for load-store bonding"),
68-
cl::init(false), cl::Hidden);
66+
UseMIPSLoadStorePairsOpt("mips-riscv-load-store-pairs",
67+
cl::desc("RISCV: Optimize for load-store bonding"),
68+
cl::init(false), cl::Hidden);
6969

7070
static cl::opt<bool>
7171
UseCCMovInsn("riscv-ccmov", cl::desc("RISCV: Use 'mips.ccmov' instruction"),
@@ -249,9 +249,9 @@ void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
249249
}
250250

251251
bool RISCVSubtarget::useLoadStorePairs() const {
252-
return UseLoadStorePairsOpt && HasMIPSLSP;
252+
return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
253253
}
254254

255255
bool RISCVSubtarget::useCCMovInsn() const {
256-
return UseCCMovInsn && HasVendorMIPSCMove;
256+
return UseCCMovInsn && HasVendorXMIPSCMove;
257257
}

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -392,7 +392,7 @@ class RISCVPassConfig : public TargetPassConfig {
392392

393393
return DAG;
394394
}
395-
395+
396396
void addIRPasses() override;
397397
bool addPreISel() override;
398398
void addCodeGenPrepare() override;

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1083,6 +1083,8 @@ R"(All available -march extensions for RISC-V
10831083
xcvmac 1.0
10841084
xcvmem 1.0
10851085
xcvsimd 1.0
1086+
xmipscmove 1.0
1087+
xmipslsp 1.0
10861088
xsfcease 1.0
10871089
xsfvcp 1.0
10881090
xsfvfnrclipxfqf 1.0

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