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[RISCV] Add ISel patterns for Xqcia instructions (#136548)
This patch adds instruction selection patterns for generating the integer arithmetic instructions.
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -422,6 +422,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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else if (!Subtarget.hasVendorXTHeadCondMov())
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setOperationAction(ISD::SELECT, XLenVT, Custom);
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if (Subtarget.hasVendorXqcia() && !Subtarget.is64Bit()) {
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setOperationAction(ISD::UADDSAT, MVT::i32, Legal);
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setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
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setOperationAction(ISD::USUBSAT, MVT::i32, Legal);
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setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
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setOperationAction(ISD::SSHLSAT, MVT::i32, Legal);
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setOperationAction(ISD::USHLSAT, MVT::i32, Legal);
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}
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static const unsigned FPLegalNodeTypes[] = {
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ISD::FMINNUM, ISD::FMAXNUM, ISD::FMINIMUMNUM,
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ISD::FMAXIMUMNUM, ISD::LRINT, ISD::LLRINT,

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

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@@ -1247,6 +1247,10 @@ class PatGprNoX0Simm32NoSimm26<SDPatternOperator OpNode, RVInst48 Inst>
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: Pat<(i32 (OpNode (i32 GPRNoX0:$rs1), simm32_nosimm26:$imm)),
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(Inst GPRNoX0:$rs1, simm32_nosimm26:$imm)>;
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class PatGprNoX0GprNoX0<SDPatternOperator OpNode, RVInstR Inst>
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: Pat<(i32 (OpNode (i32 GPRNoX0:$rs1), (i32 GPRNoX0:$rs2))),
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(Inst GPRNoX0:$rs1, GPRNoX0:$rs2)>;
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class QC48LdPat<PatFrag LoadOp, RVInst48 Inst>
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: Pat<(i32 (LoadOp (AddLike (i32 GPR:$rs1), simm26_nosimm12:$imm26))),
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(Inst GPR:$rs1, simm26_nosimm12:$imm26)>;
@@ -1308,5 +1312,14 @@ let Predicates = [HasVendorXqcisls, IsRV32], AddedComplexity = 1 in {
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def : QCScaledStPat<store, QC_SRW>;
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} // Predicates = [HasVendorXqcisls, IsRV32], AddedComplexity = 1
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let Predicates = [HasVendorXqcia, IsRV32] in {
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def : PatGprNoX0GprNoX0<saddsat, QC_ADDSAT>;
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def : PatGprNoX0GprNoX0<uaddsat, QC_ADDUSAT>;
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def : PatGprNoX0GprNoX0<ssubsat, QC_SUBSAT>;
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def : PatGprNoX0GprNoX0<usubsat, QC_SUBUSAT>;
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def : PatGprNoX0GprNoX0<ushlsat, QC_SHLUSAT>;
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def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
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} // Predicates = [HasVendorXqcia, IsRV32]
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let Predicates = [HasVendorXqciint, IsRV32] in
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def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;

‎llvm/test/CodeGen/RISCV/xqcia.ll

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@@ -0,0 +1,128 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Test that we are able to generate the Xqcia instructions
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=RV32IXQCIA
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define i32 @addsat(i32 %a, i32 %b) {
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; RV32I-LABEL: addsat:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: slt a2, a0, a2
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; RV32I-NEXT: slti a1, a1, 0
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; RV32I-NEXT: beq a1, a2, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srai a0, a0, 31
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: ret
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;
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; RV32IXQCIA-LABEL: addsat:
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; RV32IXQCIA: # %bb.0:
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; RV32IXQCIA-NEXT: qc.addsat a0, a0, a1
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; RV32IXQCIA-NEXT: ret
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%saddsat = tail call i32 @llvm.sadd.sat.i32(i32 %a,i32 %b)
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ret i32 %saddsat
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}
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define i32 @addusat(i32 %a, i32 %b) {
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; RV32I-LABEL: addusat:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a1, a0, a1
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: neg a0, a0
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIA-LABEL: addusat:
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; RV32IXQCIA: # %bb.0:
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; RV32IXQCIA-NEXT: qc.addusat a0, a0, a1
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; RV32IXQCIA-NEXT: ret
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%uaddsat = tail call i32 @llvm.uadd.sat.i32(i32 %a,i32 %b)
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ret i32 %uaddsat
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}
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define i32 @subsat(i32 %a, i32 %b) {
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; RV32I-LABEL: subsat:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: sgtz a3, a1
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: slt a1, a0, a2
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; RV32I-NEXT: beq a3, a1, .LBB2_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srai a0, a0, 31
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: ret
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;
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; RV32IXQCIA-LABEL: subsat:
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; RV32IXQCIA: # %bb.0:
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; RV32IXQCIA-NEXT: qc.subsat a0, a0, a1
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; RV32IXQCIA-NEXT: ret
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%ssubsat = tail call i32 @llvm.ssub.sat.i32(i32 %a,i32 %b)
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ret i32 %ssubsat
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}
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define i32 @subusat(i32 %a, i32 %b) {
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; RV32I-LABEL: subusat:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a1, a0, a1
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IXQCIA-LABEL: subusat:
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; RV32IXQCIA: # %bb.0:
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; RV32IXQCIA-NEXT: qc.subusat a0, a0, a1
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; RV32IXQCIA-NEXT: ret
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%usubsat = tail call i32 @llvm.usub.sat.i32(i32 %a,i32 %b)
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ret i32 %usubsat
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}
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define i32 @shlusat(i32 %a, i32 %b) {
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; RV32I-LABEL: shlusat:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sll a2, a0, a1
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; RV32I-NEXT: srl a1, a2, a1
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV32IXQCIA-LABEL: shlusat:
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; RV32IXQCIA: # %bb.0:
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; RV32IXQCIA-NEXT: qc.shlusat a0, a0, a1
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; RV32IXQCIA-NEXT: ret
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%ushlsat = tail call i32 @llvm.ushl.sat.i32(i32 %a,i32 %b)
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ret i32 %ushlsat
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}
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define i32 @shlsat(i32 %a, i32 %b) {
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; RV32I-LABEL: shlsat:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a2, a0
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: sra a1, a0, a1
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; RV32I-NEXT: beq a2, a1, .LBB5_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srai a2, a2, 31
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; RV32I-NEXT: lui a0, 524288
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: xor a0, a2, a0
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; RV32I-NEXT: .LBB5_2:
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; RV32I-NEXT: ret
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;
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; RV32IXQCIA-LABEL: shlsat:
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; RV32IXQCIA: # %bb.0:
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; RV32IXQCIA-NEXT: qc.shlsat a0, a0, a1
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; RV32IXQCIA-NEXT: ret
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%sshlsat = tail call i32 @llvm.sshl.sat.i32(i32 %a,i32 %b)
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ret i32 %sshlsat
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}

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