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[RISCV] Add CFI information for vector callee-saved registers
Currently the CFI offset for RVV registers are not handled entirely, this patch add those information for either stack unwinding or debugger to work correctly on RVV callee-saved stack object. Depends On D154576 Differential Revision: https://reviews.llvm.org/D156846
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‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 127 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -435,6 +435,32 @@ void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
435435
Flag, getStackAlign());
436436
}
437437

438+
static void appendScalableVectorExpression(SmallVectorImpl<char> &Expr,
439+
int FixedOffset, int ScalableOffset,
440+
unsigned DwarfVlenb,
441+
llvm::raw_string_ostream &Comment) {
442+
uint8_t buffer[16];
443+
if (FixedOffset) {
444+
Expr.push_back(dwarf::DW_OP_consts);
445+
Expr.append(buffer, buffer + encodeSLEB128(FixedOffset, buffer));
446+
Expr.push_back((uint8_t)dwarf::DW_OP_plus);
447+
Comment << (FixedOffset < 0 ? " - " : " + ") << std::abs(FixedOffset);
448+
}
449+
450+
Expr.push_back((uint8_t)dwarf::DW_OP_consts);
451+
Expr.append(buffer, buffer + encodeSLEB128(ScalableOffset, buffer));
452+
453+
Expr.push_back((uint8_t)dwarf::DW_OP_bregx);
454+
Expr.append(buffer, buffer + encodeULEB128(DwarfVlenb, buffer));
455+
Expr.push_back(0);
456+
457+
Expr.push_back((uint8_t)dwarf::DW_OP_mul);
458+
Expr.push_back((uint8_t)dwarf::DW_OP_plus);
459+
460+
Comment << (ScalableOffset < 0 ? " - " : " + ") << std::abs(ScalableOffset)
461+
<< " * vlenb";
462+
}
463+
438464
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI,
439465
Register Reg,
440466
uint64_t FixedOffset,
@@ -452,29 +478,40 @@ static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI,
452478
else
453479
Comment << printReg(Reg, &TRI);
454480

455-
uint8_t buffer[16];
456-
if (FixedOffset) {
457-
Expr.push_back(dwarf::DW_OP_consts);
458-
Expr.append(buffer, buffer + encodeSLEB128(FixedOffset, buffer));
459-
Expr.push_back((uint8_t)dwarf::DW_OP_plus);
460-
Comment << " + " << FixedOffset;
461-
}
481+
appendScalableVectorExpression(
482+
Expr, FixedOffset, ScalableOffset,
483+
TRI.getDwarfRegNum(RISCV::VLENB, true), Comment);
462484

463-
Expr.push_back((uint8_t)dwarf::DW_OP_consts);
464-
Expr.append(buffer, buffer + encodeSLEB128(ScalableOffset, buffer));
485+
SmallString<64> DefCfaExpr;
486+
uint8_t buffer[16];
487+
DefCfaExpr.push_back(dwarf::DW_CFA_def_cfa_expression);
488+
DefCfaExpr.append(buffer, buffer + encodeULEB128(Expr.size(), buffer));
489+
DefCfaExpr.append(Expr.str());
465490

466-
unsigned DwarfVlenb = TRI.getDwarfRegNum(RISCV::VLENB, true);
467-
Expr.push_back((uint8_t)dwarf::DW_OP_bregx);
468-
Expr.append(buffer, buffer + encodeULEB128(DwarfVlenb, buffer));
469-
Expr.push_back(0);
491+
return MCCFIInstruction::createEscape(nullptr, DefCfaExpr.str(), SMLoc(),
492+
Comment.str());
493+
}
470494

471-
Expr.push_back((uint8_t)dwarf::DW_OP_mul);
472-
Expr.push_back((uint8_t)dwarf::DW_OP_plus);
495+
static MCCFIInstruction createDefCFAOffset(const TargetRegisterInfo &TRI,
496+
Register Reg,
497+
uint64_t FixedOffset,
498+
uint64_t ScalableOffset) {
499+
assert(ScalableOffset != 0 && "Did not need to adjust CFA for RVV");
500+
SmallString<64> Expr;
501+
std::string CommentBuffer;
502+
llvm::raw_string_ostream Comment(CommentBuffer);
503+
Comment << printReg(Reg, &TRI) << " @ cfa";
473504

474-
Comment << " + " << ScalableOffset << " * vlenb";
505+
// Build up the expression (FixedOffset + ScalableOffset * VLENB).
506+
appendScalableVectorExpression(
507+
Expr, FixedOffset, ScalableOffset,
508+
TRI.getDwarfRegNum(RISCV::VLENB, true), Comment);
475509

476510
SmallString<64> DefCfaExpr;
477-
DefCfaExpr.push_back(dwarf::DW_CFA_def_cfa_expression);
511+
uint8_t buffer[16];
512+
unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true);
513+
DefCfaExpr.push_back(dwarf::DW_CFA_expression);
514+
DefCfaExpr.append(buffer, buffer + encodeULEB128(DwarfReg, buffer));
478515
DefCfaExpr.append(buffer, buffer + encodeULEB128(Expr.size(), buffer));
479516
DefCfaExpr.append(Expr.str());
480517

@@ -669,6 +706,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
669706
.addCFIIndex(CFIIndex)
670707
.setMIFlag(MachineInstr::FrameSetup);
671708
}
709+
710+
std::advance(MBBI, getRVVCalleeSavedInfo(MF, CSI).size());
711+
emitCalleeSavedRVVPrologCFI(MBB, MBBI, hasFP(MF));
672712
}
673713

674714
if (hasFP(MF)) {
@@ -755,6 +795,9 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
755795
uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
756796
uint64_t RVVStackSize = RVFI->getRVVStackSize();
757797

798+
if (RVVStackSize)
799+
emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
800+
758801
// Restore the stack pointer using the value of the frame pointer. Only
759802
// necessary if the stack pointer was modified, meaning the stack size is
760803
// unknown.
@@ -777,6 +820,15 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
777820
MachineInstr::FrameDestroy);
778821
}
779822

823+
if (RVVStackSize) {
824+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
825+
nullptr, RI->getDwarfRegNum(SPReg, true), RealStackSize));
826+
BuildMI(MBB, LastFrameDestroy, DL,
827+
STI.getInstrInfo()->get(TargetOpcode::CFI_INSTRUCTION))
828+
.addCFIIndex(CFIIndex)
829+
.setMIFlags(MachineInstr::FrameDestroy);
830+
}
831+
780832
uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
781833
if (FirstSPAdjustAmount) {
782834
uint64_t SecondSPAdjustAmount =
@@ -1528,6 +1580,64 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
15281580
return true;
15291581
}
15301582

1583+
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
1584+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
1585+
MachineFunction *MF = MBB.getParent();
1586+
const MachineFrameInfo &MFI = MF->getFrameInfo();
1587+
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1588+
const TargetInstrInfo &TII = *STI.getInstrInfo();
1589+
DebugLoc DL = MBB.findDebugLoc(MI);
1590+
1591+
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1592+
if (RVVCSI.empty())
1593+
return;
1594+
1595+
uint64_t FixedSize = getStackSizeWithRVVPadding(*MF) +
1596+
RVFI->getLibCallStackSize() +
1597+
RVFI->getRVPushStackSize();
1598+
if (!HasFP) {
1599+
uint64_t ScalarLocalVarSize =
1600+
MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
1601+
RVFI->getRVPushStackSize() - RVFI->getVarArgsSaveSize() +
1602+
RVFI->getRVVPadding();
1603+
FixedSize -= ScalarLocalVarSize;
1604+
}
1605+
1606+
for (auto &CS: RVVCSI) {
1607+
// Insert the spill to the stack frame.
1608+
int FI = CS.getFrameIdx();
1609+
if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector) {
1610+
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1611+
*STI.getRegisterInfo(), CS.getReg(),
1612+
-FixedSize, MFI.getObjectOffset(FI) / 8));
1613+
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1614+
.addCFIIndex(CFIIndex)
1615+
.setMIFlag(MachineInstr::FrameSetup);
1616+
}
1617+
}
1618+
}
1619+
1620+
void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
1621+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
1622+
MachineFunction *MF = MBB.getParent();
1623+
const MachineFrameInfo &MFI = MF->getFrameInfo();
1624+
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
1625+
const TargetInstrInfo &TII = *STI.getInstrInfo();
1626+
DebugLoc DL = MBB.findDebugLoc(MI);
1627+
1628+
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1629+
if (RVVCSI.empty())
1630+
return;
1631+
1632+
for (const auto &CS : RVVCSI) {
1633+
unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
1634+
nullptr, TRI.getDwarfRegNum(CS.getReg(), true)));
1635+
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1636+
.addCFIIndex(CFIIndex)
1637+
.setMIFlags(MachineInstr::FrameDestroy);
1638+
}
1639+
}
1640+
15311641
bool RISCVFrameLowering::restoreCalleeSavedRegisters(
15321642
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
15331643
MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,11 @@ class RISCVFrameLowering : public TargetFrameLowering {
8888
void adjustStackForRVV(MachineFunction &MF, MachineBasicBlock &MBB,
8989
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
9090
int64_t Amount, MachineInstr::MIFlag Flag) const;
91+
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
92+
MachineBasicBlock::iterator MI,
93+
bool HasFP) const;
94+
void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
95+
MachineBasicBlock::iterator MI) const;
9196
std::pair<int64_t, Align>
9297
assignRVVStackObjectOffsets(MachineFunction &MF) const;
9398
};

‎llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ define void @_Z3foov() {
8585
; CHECK-NEXT: li a1, 10
8686
; CHECK-NEXT: mul a0, a0, a1
8787
; CHECK-NEXT: add sp, sp, a0
88+
; CHECK-NEXT: .cfi_def_cfa sp, 16
8889
; CHECK-NEXT: addi sp, sp, 16
8990
; CHECK-NEXT: ret
9091
entry:

‎llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,7 @@ define i64 @ctz_nxv8i1_no_range(<vscale x 8 x i16> %a) {
104104
; RV32-NEXT: csrr a2, vlenb
105105
; RV32-NEXT: slli a2, a2, 1
106106
; RV32-NEXT: add sp, sp, a2
107+
; RV32-NEXT: .cfi_def_cfa sp, 48
107108
; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
108109
; RV32-NEXT: addi sp, sp, 48
109110
; RV32-NEXT: ret

‎llvm/test/CodeGen/RISCV/pr69586.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -763,6 +763,7 @@ define void @test(ptr %0, ptr %1, i64 %2) {
763763
; NOREMAT-NEXT: li a1, 6
764764
; NOREMAT-NEXT: mul a0, a0, a1
765765
; NOREMAT-NEXT: add sp, sp, a0
766+
; NOREMAT-NEXT: .cfi_def_cfa sp, 400
766767
; NOREMAT-NEXT: ld ra, 392(sp) # 8-byte Folded Reload
767768
; NOREMAT-NEXT: ld s0, 384(sp) # 8-byte Folded Reload
768769
; NOREMAT-NEXT: ld s1, 376(sp) # 8-byte Folded Reload

‎llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ define void @last_chance_recoloring_failure() {
7272
; CHECK-NEXT: csrr a0, vlenb
7373
; CHECK-NEXT: slli a0, a0, 4
7474
; CHECK-NEXT: add sp, sp, a0
75+
; CHECK-NEXT: .cfi_def_cfa sp, 32
7576
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
7677
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
7778
; CHECK-NEXT: addi sp, sp, 32
@@ -133,6 +134,7 @@ define void @last_chance_recoloring_failure() {
133134
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
134135
; SUBREGLIVENESS-NEXT: slli a0, a0, 4
135136
; SUBREGLIVENESS-NEXT: add sp, sp, a0
137+
; SUBREGLIVENESS-NEXT: .cfi_def_cfa sp, 32
136138
; SUBREGLIVENESS-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
137139
; SUBREGLIVENESS-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
138140
; SUBREGLIVENESS-NEXT: addi sp, sp, 32

‎llvm/test/CodeGen/RISCV/rvv-cfi-info.ll

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,119 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s \
3+
; RUN: | FileCheck -check-prefix=OMIT-FP %s
4+
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs -frame-pointer=all < %s \
5+
; RUN: | FileCheck -check-prefix=NO-OMIT-FP %s
6+
7+
define riscv_vector_cc <vscale x 1 x i32> @test_vector_callee_cfi(<vscale x 1 x i32> %va) {
8+
; OMIT-FP-LABEL: test_vector_callee_cfi:
9+
; OMIT-FP: # %bb.0: # %entry
10+
; OMIT-FP-NEXT: addi sp, sp, -16
11+
; OMIT-FP-NEXT: .cfi_def_cfa_offset 16
12+
; OMIT-FP-NEXT: csrr a0, vlenb
13+
; OMIT-FP-NEXT: slli a0, a0, 3
14+
; OMIT-FP-NEXT: sub sp, sp, a0
15+
; OMIT-FP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
16+
; OMIT-FP-NEXT: csrr a0, vlenb
17+
; OMIT-FP-NEXT: li a1, 6
18+
; OMIT-FP-NEXT: mul a0, a0, a1
19+
; OMIT-FP-NEXT: add a0, sp, a0
20+
; OMIT-FP-NEXT: addi a0, a0, 16
21+
; OMIT-FP-NEXT: vs1r.v v1, (a0) # Unknown-size Folded Spill
22+
; OMIT-FP-NEXT: csrr a0, vlenb
23+
; OMIT-FP-NEXT: slli a0, a0, 2
24+
; OMIT-FP-NEXT: add a0, sp, a0
25+
; OMIT-FP-NEXT: addi a0, a0, 16
26+
; OMIT-FP-NEXT: vs2r.v v2, (a0) # Unknown-size Folded Spill
27+
; OMIT-FP-NEXT: addi a0, sp, 16
28+
; OMIT-FP-NEXT: vs4r.v v4, (a0) # Unknown-size Folded Spill
29+
; OMIT-FP-NEXT: .cfi_escape 0x10, 0x61, 0x08, 0x11, 0x7e, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v1 @ cfa - 2 * vlenb
30+
; OMIT-FP-NEXT: .cfi_escape 0x10, 0x62, 0x08, 0x11, 0x7c, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v2m2 @ cfa - 4 * vlenb
31+
; OMIT-FP-NEXT: .cfi_escape 0x10, 0x64, 0x08, 0x11, 0x78, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v4m4 @ cfa - 8 * vlenb
32+
; OMIT-FP-NEXT: #APP
33+
; OMIT-FP-NEXT: #NO_APP
34+
; OMIT-FP-NEXT: csrr a0, vlenb
35+
; OMIT-FP-NEXT: li a1, 6
36+
; OMIT-FP-NEXT: mul a0, a0, a1
37+
; OMIT-FP-NEXT: add a0, sp, a0
38+
; OMIT-FP-NEXT: addi a0, a0, 16
39+
; OMIT-FP-NEXT: vl1r.v v1, (a0) # Unknown-size Folded Reload
40+
; OMIT-FP-NEXT: csrr a0, vlenb
41+
; OMIT-FP-NEXT: slli a0, a0, 2
42+
; OMIT-FP-NEXT: add a0, sp, a0
43+
; OMIT-FP-NEXT: addi a0, a0, 16
44+
; OMIT-FP-NEXT: vl2r.v v2, (a0) # Unknown-size Folded Reload
45+
; OMIT-FP-NEXT: addi a0, sp, 16
46+
; OMIT-FP-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload
47+
; OMIT-FP-NEXT: .cfi_restore v1
48+
; OMIT-FP-NEXT: .cfi_restore v2
49+
; OMIT-FP-NEXT: .cfi_restore v4
50+
; OMIT-FP-NEXT: csrr a0, vlenb
51+
; OMIT-FP-NEXT: slli a0, a0, 3
52+
; OMIT-FP-NEXT: add sp, sp, a0
53+
; OMIT-FP-NEXT: .cfi_def_cfa sp, 16
54+
; OMIT-FP-NEXT: addi sp, sp, 16
55+
; OMIT-FP-NEXT: ret
56+
;
57+
; NO-OMIT-FP-LABEL: test_vector_callee_cfi:
58+
; NO-OMIT-FP: # %bb.0: # %entry
59+
; NO-OMIT-FP-NEXT: addi sp, sp, -32
60+
; NO-OMIT-FP-NEXT: .cfi_def_cfa_offset 32
61+
; NO-OMIT-FP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
62+
; NO-OMIT-FP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
63+
; NO-OMIT-FP-NEXT: .cfi_offset ra, -8
64+
; NO-OMIT-FP-NEXT: .cfi_offset s0, -16
65+
; NO-OMIT-FP-NEXT: addi s0, sp, 32
66+
; NO-OMIT-FP-NEXT: .cfi_def_cfa s0, 0
67+
; NO-OMIT-FP-NEXT: csrr a0, vlenb
68+
; NO-OMIT-FP-NEXT: slli a0, a0, 3
69+
; NO-OMIT-FP-NEXT: sub sp, sp, a0
70+
; NO-OMIT-FP-NEXT: csrr a0, vlenb
71+
; NO-OMIT-FP-NEXT: slli a0, a0, 1
72+
; NO-OMIT-FP-NEXT: sub a0, s0, a0
73+
; NO-OMIT-FP-NEXT: addi a0, a0, -32
74+
; NO-OMIT-FP-NEXT: vs1r.v v1, (a0) # Unknown-size Folded Spill
75+
; NO-OMIT-FP-NEXT: csrr a0, vlenb
76+
; NO-OMIT-FP-NEXT: slli a0, a0, 2
77+
; NO-OMIT-FP-NEXT: sub a0, s0, a0
78+
; NO-OMIT-FP-NEXT: addi a0, a0, -32
79+
; NO-OMIT-FP-NEXT: vs2r.v v2, (a0) # Unknown-size Folded Spill
80+
; NO-OMIT-FP-NEXT: csrr a0, vlenb
81+
; NO-OMIT-FP-NEXT: slli a0, a0, 3
82+
; NO-OMIT-FP-NEXT: sub a0, s0, a0
83+
; NO-OMIT-FP-NEXT: addi a0, a0, -32
84+
; NO-OMIT-FP-NEXT: vs4r.v v4, (a0) # Unknown-size Folded Spill
85+
; NO-OMIT-FP-NEXT: .cfi_escape 0x10, 0x61, 0x0b, 0x11, 0x60, 0x22, 0x11, 0x7e, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v1 @ cfa - 32 - 2 * vlenb
86+
; NO-OMIT-FP-NEXT: .cfi_escape 0x10, 0x62, 0x0b, 0x11, 0x60, 0x22, 0x11, 0x7c, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v2m2 @ cfa - 32 - 4 * vlenb
87+
; NO-OMIT-FP-NEXT: .cfi_escape 0x10, 0x64, 0x0b, 0x11, 0x60, 0x22, 0x11, 0x78, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v4m4 @ cfa - 32 - 8 * vlenb
88+
; NO-OMIT-FP-NEXT: #APP
89+
; NO-OMIT-FP-NEXT: #NO_APP
90+
; NO-OMIT-FP-NEXT: csrr a0, vlenb
91+
; NO-OMIT-FP-NEXT: slli a0, a0, 1
92+
; NO-OMIT-FP-NEXT: sub a0, s0, a0
93+
; NO-OMIT-FP-NEXT: addi a0, a0, -32
94+
; NO-OMIT-FP-NEXT: vl1r.v v1, (a0) # Unknown-size Folded Reload
95+
; NO-OMIT-FP-NEXT: csrr a0, vlenb
96+
; NO-OMIT-FP-NEXT: slli a0, a0, 2
97+
; NO-OMIT-FP-NEXT: sub a0, s0, a0
98+
; NO-OMIT-FP-NEXT: addi a0, a0, -32
99+
; NO-OMIT-FP-NEXT: vl2r.v v2, (a0) # Unknown-size Folded Reload
100+
; NO-OMIT-FP-NEXT: csrr a0, vlenb
101+
; NO-OMIT-FP-NEXT: slli a0, a0, 3
102+
; NO-OMIT-FP-NEXT: sub a0, s0, a0
103+
; NO-OMIT-FP-NEXT: addi a0, a0, -32
104+
; NO-OMIT-FP-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload
105+
; NO-OMIT-FP-NEXT: .cfi_restore v1
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; NO-OMIT-FP-NEXT: .cfi_restore v2
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; NO-OMIT-FP-NEXT: .cfi_restore v4
108+
; NO-OMIT-FP-NEXT: addi sp, s0, -32
109+
; NO-OMIT-FP-NEXT: .cfi_def_cfa sp, 32
110+
; NO-OMIT-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; NO-OMIT-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; NO-OMIT-FP-NEXT: addi sp, sp, 32
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; NO-OMIT-FP-NEXT: ret
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entry:
115+
call void asm sideeffect "",
116+
"~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"()
117+
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ret <vscale x 1 x i32> %va
119+
}

‎llvm/test/CodeGen/RISCV/rvv/abs-vp.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -650,6 +650,7 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
650650
; CHECK-NEXT: csrr a0, vlenb
651651
; CHECK-NEXT: slli a0, a0, 4
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; CHECK-NEXT: add sp, sp, a0
653+
; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i64> @llvm.vp.abs.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)

‎llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ define <vscale x 1 x i64> @access_fixed_and_vector_objects(ptr %val) {
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; RV64IV-NEXT: csrr a0, vlenb
4747
; RV64IV-NEXT: slli a0, a0, 1
4848
; RV64IV-NEXT: add sp, sp, a0
49+
; RV64IV-NEXT: .cfi_def_cfa sp, 528
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; RV64IV-NEXT: addi sp, sp, 528
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; RV64IV-NEXT: ret
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%local = alloca i64

‎llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,7 @@ body: |
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; CHECK-NEXT: VS1R_V killed renamable $v8, killed renamable $x10
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; CHECK-NEXT: $x2 = frame-destroy ADDI $x8, -2048
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; CHECK-NEXT: $x2 = frame-destroy ADDI killed $x2, -224
53+
; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 2272
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; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240
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; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
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; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)

‎llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-array.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ define void @test(ptr %addr) {
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; CHECK-NEXT: csrrs a0, vlenb, zero
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; CHECK-NEXT: slli a0, a0, 2
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; CHECK-NEXT: add sp, sp, a0
33+
; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:

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