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[AMDGPU] Remove GDS and GWS for GFX12 (#76148)
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9 files changed

+45
-11
lines changed

9 files changed

+45
-11
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1100,8 +1100,8 @@ def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
11001100
FeatureVOP3Literal, FeatureDPP8,
11011101
FeatureNoDataDepHazard, FeaturePkFmacF16Inst,
11021102
FeatureA16, FeatureFastDenormalF32, FeatureG16,
1103-
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess, FeatureGDS,
1104-
FeatureGWS, FeatureTrue16BitInsts
1103+
FeatureUnalignedBufferAccess, FeatureUnalignedDSAccess,
1104+
FeatureTrue16BitInsts
11051105
]
11061106
>;
11071107

‎llvm/lib/Target/AMDGPU/DSInstructions.td

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1147,7 +1147,8 @@ def : GCNPat <
11471147
>;
11481148
} // End SubtargetPredicate = HasAtomicDsPkAdd16Insts
11491149

1150-
def : Pat <
1150+
let OtherPredicates = [HasGDS] in
1151+
def : GCNPat <
11511152
(SIds_ordered_count i32:$value, i16:$offset),
11521153
(DS_ORDERED_COUNT $value, (as_i16imm $offset))
11531154
>;
@@ -1189,7 +1190,8 @@ def : GCNPat <
11891190
//===----------------------------------------------------------------------===//
11901191

11911192
class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
1192-
string opName = ps.Mnemonic>
1193+
string opName = ps.Mnemonic,
1194+
bit hasGFX12Enc = 0>
11931195
: DS_Real<ps, opName>, SIMCInstr <ps.Mnemonic, ef> {
11941196

11951197
let Inst{7-0} = !if(ps.has_offset0, offset0, 0);
@@ -1201,6 +1203,8 @@ class Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<8> op, DS_Pseudo ps, int ef,
12011203
let Inst{47-40} = !if(ps.has_data0, data0{7-0}, 0);
12021204
let Inst{55-48} = !if(ps.has_data1, data1{7-0}, 0);
12031205
let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
1206+
1207+
let gds = !if(hasGFX12Enc, 0, ?);
12041208
}
12051209

12061210
//===----------------------------------------------------------------------===//
@@ -1212,15 +1216,15 @@ let AssemblerPredicate = isGFX12Plus, DecoderNamespace = "GFX12" in {
12121216
defvar ps = !cast<DS_Pseudo>(NAME);
12131217
def _gfx12 :
12141218
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, ps, SIEncodingFamily.GFX12,
1215-
ps.Mnemonic>;
1219+
ps.Mnemonic, 1>;
12161220
}
12171221

12181222
multiclass DS_Real_Renamed_gfx12<bits<8> op, DS_Pseudo backing_pseudo,
12191223
string real_name> {
12201224
def _gfx12 :
12211225
Base_DS_Real_gfx6_gfx7_gfx10_gfx11_gfx12<op, backing_pseudo,
12221226
SIEncodingFamily.GFX12,
1223-
real_name>,
1227+
real_name, 1>,
12241228
MnemonicAlias<backing_pseudo.Mnemonic, real_name>,
12251229
Requires<[isGFX12Plus]>;
12261230
}

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -702,6 +702,11 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
702702
AMDGPU::OpName::src2_modifiers);
703703
}
704704

705+
if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) &&
706+
!AMDGPU::hasGDS(STI)) {
707+
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds);
708+
}
709+
705710
if (Res && (MCII->get(MI.getOpcode()).TSFlags &
706711
(SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) {
707712
int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4983,6 +4983,14 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
49834983
}
49844984
}
49854985

4986+
if (isDS(MI) && !ST.hasGDS()) {
4987+
const MachineOperand *GDSOp = getNamedOperand(MI, AMDGPU::OpName::gds);
4988+
if (GDSOp && GDSOp->getImm() != 0) {
4989+
ErrInfo = "GDS is not supported on this subtarget";
4990+
return false;
4991+
}
4992+
}
4993+
49864994
if (isImage(MI)) {
49874995
const MachineOperand *DimOp = getNamedOperand(MI, AMDGPU::OpName::dim);
49884996
if (DimOp) {

‎llvm/test/CodeGen/AMDGPU/gds-unsupported.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
; RUN: not --crash llc -march=amdgcn -mcpu=gfx90a < %s 2>&1 | FileCheck %s
2+
; RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 < %s 2>&1 | FileCheck %s
23

34
; GDS is not supported on GFX90A+
45
; CHECK: LLVM ERROR: Cannot select: {{.*}} AtomicLoadAdd

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,8 @@
11
; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
22
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
3+
; RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
4+
5+
; GFX12-ERR: LLVM ERROR: Cannot select: {{.*}} = DS_ORDERED_COUNT
36

47
; FUNC-LABEL: {{^}}ds_ordered_add:
58
; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31

‎llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: not --crash llc -march=amdgcn -mcpu=gfx1200 -run-pass=none -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX12 %s
2+
3+
---
4+
name: gds
5+
body: |
6+
bb.0:
7+
; GFX12: *** Bad machine code: GDS is not supported on this subtarget ***
8+
; GFX12: - instruction: DS_ADD_U32 %0:vgpr_32, %1:vgpr_32, 0, 1, implicit $m0, implicit $exec :: (load store acq_rel (s32), addrspace 2)
9+
DS_ADD_U32 %0:vgpr_32, %2:vgpr_32, 0, 1, implicit $m0, implicit $exec :: (load store acq_rel (s32), addrspace 2)
10+
...

‎llvm/test/MC/Disassembler/AMDGPU/decode-err.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,14 @@
3434
# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
3535
0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0
3636

37+
# this is ds_add_f32 with gds bit which is not valid on gfx12+
38+
# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding
39+
0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00
40+
3741
# this is image_msaa_load where samp field for gfx12 VSAMPLE is not all zeros
3842
# GFX12: [[@LINE+1]]:1: warning: invalid instruction encoding
3943
0x06,0x00,0x46,0xe4,0x01,0x10,0x80,0x00,0x05,0x06,0x07,0x00
44+
45+
# This is ds_read_b32 with gds bit which is not valid on gfx90a.
46+
# GFX90A: [[@LINE+1]]:1: warning: invalid instruction encoding
47+
0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00

‎llvm/test/MC/Disassembler/AMDGPU/gfx90a_features.txt

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -773,8 +773,3 @@
773773

774774
# GFX90A: flat_atomic_min_f64 v[0:1], v[0:1], v[2:3] glc ; encoding: [0x00,0x00,0x41,0xdd,0x00,0x02,0x00,0x00]
775775
0x00,0x00,0x41,0xdd,0x00,0x02,0x00,0x00
776-
777-
# Disassembler still decodes the gds modifier even though the assembler does
778-
# not accept it.
779-
# GFX90A: ds_read_b32 v0, v1 gds ; encoding: [0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00]
780-
0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00

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