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[SystemZ] Handle index-only addresses in (dis)assembler
Most addresses in SystemZ instructions take two registers, an index register and a base register. However, either of those can be omitted. If there is just a single register, this usually is taken as the base register - however, there are certain rare cases where you specifically want to use an index register but no base register. This is currently not handled consistently by the assembler / disassembler. Fix this by - always emitting a dummy 0 as base register for index- only addresses - correctly handle dummy 0 as indicating no base register when parsing an address This is compatible with current GNU binutils behavior.
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7 files changed

+49
-26
lines changed

7 files changed

+49
-26
lines changed

‎llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1123,7 +1123,7 @@ ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
11231123
if (HaveReg1) {
11241124
if (parseAddressRegister(Reg1))
11251125
return ParseStatus::Failure;
1126-
Base = Regs[Reg1.Num];
1126+
Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
11271127
}
11281128
// There must be no Reg2.
11291129
if (HaveReg2)
@@ -1137,23 +1137,23 @@ ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
11371137
// If the are two registers, the first one is the index and the
11381138
// second is the base.
11391139
if (HaveReg2)
1140-
Index = Regs[Reg1.Num];
1140+
Index = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
11411141
else
1142-
Base = Regs[Reg1.Num];
1142+
Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
11431143
}
11441144
// If we have Reg2, it must be an address register.
11451145
if (HaveReg2) {
11461146
if (parseAddressRegister(Reg2))
11471147
return ParseStatus::Failure;
1148-
Base = Regs[Reg2.Num];
1148+
Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
11491149
}
11501150
break;
11511151
case BDLMem:
11521152
// If we have Reg2, it must be an address register.
11531153
if (HaveReg2) {
11541154
if (parseAddressRegister(Reg2))
11551155
return ParseStatus::Failure;
1156-
Base = Regs[Reg2.Num];
1156+
Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
11571157
}
11581158
// We cannot support base+index addressing.
11591159
if (HaveReg1 && HaveReg2)
@@ -1171,7 +1171,7 @@ ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
11711171
if (HaveReg2) {
11721172
if (parseAddressRegister(Reg2))
11731173
return ParseStatus::Failure;
1174-
Base = Regs[Reg2.Num];
1174+
Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
11751175
}
11761176
break;
11771177
case BDVMem:
@@ -1183,7 +1183,7 @@ ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
11831183
if (HaveReg2) {
11841184
if (parseAddressRegister(Reg2))
11851185
return ParseStatus::Failure;
1186-
Base = Regs[Reg2.Num];
1186+
Base = Reg2.Num == 0 ? 0 : Regs[Reg2.Num];
11871187
}
11881188
break;
11891189
}

‎llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,11 +32,12 @@ void SystemZInstPrinter::printAddress(const MCAsmInfo *MAI, MCRegister Base,
3232
O << '(';
3333
if (Index) {
3434
printFormattedRegName(MAI, Index, O);
35-
if (Base)
36-
O << ',';
35+
O << ',';
3736
}
3837
if (Base)
3938
printFormattedRegName(MAI, Base, O);
39+
else
40+
O << '0';
4041
O << ')';
4142
}
4243
}

‎llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -353,9 +353,9 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
353353
}
354354
EmitToStreamer(*OutStreamer, MCInstBuilder(Op)
355355
.addReg(TargetReg)
356-
.addReg(IndexReg)
356+
.addReg(ADAReg)
357357
.addImm(Disp)
358-
.addReg(ADAReg));
358+
.addReg(IndexReg));
359359

360360
return;
361361
}

‎llvm/test/MC/Disassembler/SystemZ/insns-z13.txt

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2150,7 +2150,7 @@
21502150
# CHECK: vone %v31
21512151
0xe7 0xf0 0xff 0xff 0x08 0x44
21522152

2153-
# CHECK: vgef %v0, 0(%v0), 0
2153+
# CHECK: vgef %v0, 0(%v0,0), 0
21542154
0xe7 0x00 0x00 0x00 0x00 0x13
21552155

21562156
# CHECK: vgef %v10, 1000(%v19,%r7), 2
@@ -2159,7 +2159,7 @@
21592159
# CHECK: vgef %v31, 4095(%v31,%r15), 3
21602160
0xe7 0xff 0xff 0xff 0x3c 0x13
21612161

2162-
# CHECK: vgeg %v0, 0(%v0), 0
2162+
# CHECK: vgeg %v0, 0(%v0,0), 0
21632163
0xe7 0x00 0x00 0x00 0x00 0x12
21642164

21652165
# CHECK: vgeg %v10, 1000(%v19,%r7), 1
@@ -3959,7 +3959,7 @@
39593959
# CHECK: vscbiq %v31, %v31, %v31
39603960
0xe7 0xff 0xf0 0x00 0x4e 0xf5
39613961

3962-
# CHECK: vscef %v0, 0(%v0), 0
3962+
# CHECK: vscef %v0, 0(%v0,0), 0
39633963
0xe7 0x00 0x00 0x00 0x00 0x1b
39643964

39653965
# CHECK: vscef %v10, 1000(%v19,%r7), 2
@@ -3968,7 +3968,7 @@
39683968
# CHECK: vscef %v31, 4095(%v31,%r15), 3
39693969
0xe7 0xff 0xff 0xff 0x3c 0x1b
39703970

3971-
# CHECK: vsceg %v0, 0(%v0), 0
3971+
# CHECK: vsceg %v0, 0(%v0,0), 0
39723972
0xe7 0x00 0x00 0x00 0x00 0x1a
39733973

39743974
# CHECK: vsceg %v10, 1000(%v19,%r7), 1

‎llvm/test/MC/SystemZ/fixups.s

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -291,10 +291,10 @@
291291
vgeg %v0, src(%v0,%r1), 0
292292

293293
## Fixup for second operand only
294-
# CHECK: mvc 32(8,%r0), src # encoding: [0xd2,0x07,0x00,0x20,0b0000AAAA,A]
294+
# CHECK: mvc 32(8,%r1), src # encoding: [0xd2,0x07,0x10,0x20,0b0000AAAA,A]
295295
# CHECK-NEXT: # fixup A - offset: 4, value: src, kind: FK_390_U12Imm
296296
.align 16
297-
mvc 32(8,%r0),src
297+
mvc 32(8,%r1),src
298298

299299
##U8
300300
# CHECK: cli 0(%r1), src # encoding: [0x95,A,0x10,0x00]

‎llvm/test/MC/SystemZ/insn-good-z13.s

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2879,7 +2879,7 @@
28792879
vgbm %v31, 0
28802880
vgbm %v17, 0x1234
28812881

2882-
#CHECK: vgef %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
2882+
#CHECK: vgef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
28832883
#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
28842884
#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
28852885
#CHECK: vgef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
@@ -2893,7 +2893,7 @@
28932893
#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
28942894
#CHECK: vgef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
28952895
#CHECK: vgef %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13]
2896-
#CHECK: vgef %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
2896+
#CHECK: vgef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
28972897
#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
28982898
#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
28992899
#CHECK: vgef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
@@ -2929,7 +2929,7 @@
29292929
vgef 31, 0(0,1), 0
29302930
vgef 10, 1000(19,7), 1
29312931

2932-
#CHECK: vgeg %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
2932+
#CHECK: vgeg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
29332933
#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
29342934
#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
29352935
#CHECK: vgeg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
@@ -2943,7 +2943,7 @@
29432943
#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
29442944
#CHECK: vgeg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
29452945
#CHECK: vgeg %v0, 0(%v15,%r1), 0 # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12]
2946-
#CHECK: vgeg %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
2946+
#CHECK: vgeg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
29472947
#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
29482948
#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
29492949
#CHECK: vgeg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
@@ -5911,7 +5911,7 @@
59115911
vscbiq %v31, %v0, %v0
59125912
vscbiq %v18, %v3, %v20
59135913

5914-
#CHECK: vscef %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b]
5914+
#CHECK: vscef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b]
59155915
#CHECK: vscef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1b]
59165916
#CHECK: vscef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x1b]
59175917
#CHECK: vscef %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x1b]
@@ -5933,7 +5933,7 @@
59335933
vscef %v31, 0(%v0,%r1), 0
59345934
vscef %v10, 1000(%v19,%r7), 1
59355935

5936-
#CHECK: vsceg %v0, 0(%v0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a]
5936+
#CHECK: vsceg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a]
59375937
#CHECK: vsceg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1a]
59385938
#CHECK: vsceg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x1a]
59395939
#CHECK: vsceg %v0, 0(%v0,%r15), 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x1a]

‎llvm/test/MC/SystemZ/insn-good.s

Lines changed: 25 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8757,12 +8757,22 @@
87578757

87588758
#CHECK: l %r0, 0 # encoding: [0x58,0x00,0x00,0x00]
87598759
#CHECK: l %r0, 4095 # encoding: [0x58,0x00,0x0f,0xff]
8760-
#CHECK: l %r0, 0(%r0) # encoding: [0x58,0x00,0x00,0x00]
8760+
#CHECK: l %r0, 0 # encoding: [0x58,0x00,0x00,0x00]
8761+
#CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00]
8762+
#CHECK: l %r0, 0(%r15) # encoding: [0x58,0x00,0xf0,0x00]
8763+
#CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00]
8764+
#CHECK: l %r0, 0(%r15) # encoding: [0x58,0x00,0xf0,0x00]
8765+
#CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00]
8766+
#CHECK: l %r0, 0(%r15) # encoding: [0x58,0x00,0xf0,0x00]
87618767
#CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00]
87628768
#CHECK: l %r0, 0(%r15) # encoding: [0x58,0x00,0xf0,0x00]
8763-
#CHECK: l %r0, 4095(%r0,%r15) # encoding: [0x58,0x00,0xff,0xff]
8769+
#CHECK: l %r0, 0(%r1,0) # encoding: [0x58,0x01,0x00,0x00]
8770+
#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
8771+
#CHECK: l %r0, 0(%r1,0) # encoding: [0x58,0x01,0x00,0x00]
8772+
#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
8773+
#CHECK: l %r0, 4095(%r15) # encoding: [0x58,0x00,0xff,0xff]
87648774
#CHECK: l %r0, 4095(%r1,%r15) # encoding: [0x58,0x01,0xff,0xff]
8765-
#CHECK: l %r0, 4095(%r15,%r0) # encoding: [0x58,0x0f,0x0f,0xff]
8775+
#CHECK: l %r0, 4095(%r15,0) # encoding: [0x58,0x0f,0x0f,0xff]
87668776
#CHECK: l %r0, 4095(%r15,%r1) # encoding: [0x58,0x0f,0x1f,0xff]
87678777
#CHECK: l %r15, 0 # encoding: [0x58,0xf0,0x00,0x00]
87688778

@@ -8771,6 +8781,18 @@
87718781
l %r0, 0(%r0)
87728782
l %r0, 0(%r1)
87738783
l %r0, 0(%r15)
8784+
l %r0, 0(,%r1)
8785+
l %r0, 0(,%r15)
8786+
l %r0, 0(0,%r1)
8787+
l %r0, 0(0,%r15)
8788+
l %r0, 0(%r0,%r1)
8789+
l %r0, 0(%r0,%r15)
8790+
l %r0, 0(0,%r1)
8791+
l %r0, 0(0,%r15)
8792+
l %r0, 0(%r1,0)
8793+
l %r0, 0(%r15,0)
8794+
l %r0, 0(%r1,%r0)
8795+
l %r0, 0(%r15,%r0)
87748796
l %r0, 4095(%r0,%r15)
87758797
l %r0, 4095(%r1,%r15)
87768798
l %r0, 4095(%r15,%r0)

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