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Fix Rebase
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-74
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4 files changed

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‎clang/include/clang/Basic/arm_sme.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -788,7 +788,7 @@ defm SVREADZ_ZA32_X4 : ZAReadz<"za32", "4", "iUif", "aarch64_sme_readz", [ImmCh
788788
defm SVREADZ_ZA64_X4 : ZAReadz<"za64", "4", "lUld", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_7>]>;
789789

790790

791-
multiclass ZAReadz<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
791+
multiclass ZAReadzSingle<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
792792
let SMETargetGuard = "sme2p1" in {
793793
def NAME # _H : SInst<"svreadz_hor_" # n_suffix # "_{d}", "dim", t,
794794
MergeNone, i_prefix # "_horiz",
@@ -800,9 +800,9 @@ multiclass ZAReadz<string n_suffix, string t, string i_prefix, list<ImmCheck> ch
800800
}
801801
}
802802

803-
defm SVREADZ_ZA8 : ZAReadz<"za8", "cUc", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
804-
defm SVREADZ_ZA16 : ZAReadz<"za16", "sUshb", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_1>]>;
805-
defm SVREADZ_ZA32 : ZAReadz<"za32", "iUif", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_3>]>;
806-
defm SVREADZ_ZA64 : ZAReadz<"za64", "lUld", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_7>]>;
807-
defm SVREADZ_ZA128 : ZAReadz<"za128", "csilUcUiUsUlbhfd", "aarch64_sme_readz_q", [ImmCheck<0, ImmCheck0_15>]>;
803+
defm SVREADZ_ZA8 : ZAReadzSingle<"za8", "cUc", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_0>]>;
804+
defm SVREADZ_ZA16 : ZAReadzSingle<"za16", "sUshb", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_1>]>;
805+
defm SVREADZ_ZA32 : ZAReadzSingle<"za32", "iUif", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_3>]>;
806+
defm SVREADZ_ZA64 : ZAReadzSingle<"za64", "lUld", "aarch64_sme_readz", [ImmCheck<0, ImmCheck0_7>]>;
807+
defm SVREADZ_ZA128 : ZAReadzSingle<"za128", "csilUcUiUsUlbhfd", "aarch64_sme_readz_q", [ImmCheck<0, ImmCheck0_15>]>;
808808
} // let SVETargetGuard = InvalidMode

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 2 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -2941,23 +2941,6 @@ AArch64TargetLowering::EmitTileLoad(unsigned Opc, unsigned BaseReg,
29412941
return BB;
29422942
}
29432943

2944-
MachineBasicBlock *
2945-
AArch64TargetLowering::EmitTileMovaz(unsigned Opc, unsigned BaseReg,
2946-
MachineInstr &MI,
2947-
MachineBasicBlock *BB) const {
2948-
const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2949-
MachineInstrBuilder MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opc));
2950-
2951-
MIB.add(MI.getOperand(0)); // Output ZPR
2952-
MIB.addReg(BaseReg + MI.getOperand(1).getImm(),
2953-
RegState::Define); // Output ZA Tile
2954-
MIB.addReg(BaseReg + MI.getOperand(1).getImm()); // Input Za Tile
2955-
MIB.add(MI.getOperand(2)); // slice index register
2956-
MIB.add(MI.getOperand(3)); // slice index offset
2957-
MI.eraseFromParent(); // The pseudo is gone now.
2958-
return BB;
2959-
}
2960-
29612944
MachineBasicBlock *
29622945
AArch64TargetLowering::EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const {
29632946
const TargetInstrInfo *TII = Subtarget->getInstrInfo();
@@ -3001,17 +2984,8 @@ AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
30012984
bool HasTile = BaseReg != AArch64::ZA;
30022985
bool HasZPROut = HasTile && MI.getOperand(0).isReg();
30032986
if (HasZPROut) {
3004-
if(HasTile){
3005-
MIB.add(MI.getOperand(0)); // Output ZPR
3006-
MIB.addReg(BaseReg + MI.getOperand(1).getImm(),
3007-
RegState::Define); // Output ZA Tile
3008-
MIB.addReg(BaseReg + MI.getOperand(1).getImm()); // Input Za Tile
3009-
StartIdx += 2;
3010-
}
3011-
else{
3012-
MIB.add(MI.getOperand(0)); // Output ZPR
3013-
++StartIdx;
3014-
}
2987+
MIB.add(MI.getOperand(StartIdx)); // Output ZPR
2988+
++StartIdx;
30152989
}
30162990
if (HasTile) {
30172991
MIB.addReg(BaseReg + MI.getOperand(StartIdx).getImm(),
@@ -3134,9 +3108,6 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
31343108
return EmitZAInstr(SMEOrigInstr, AArch64::ZAB0, MI, BB);
31353109
case (AArch64::SMEMatrixTileH):
31363110
return EmitZAInstr(SMEOrigInstr, AArch64::ZAH0, MI, BB);
3137-
default:
3138-
return EmitZAInstr(SMEOrigInstr, AArch64::ZAH0, MI, BB,
3139-
}
31403111
case (AArch64::SMEMatrixTileS):
31413112
return EmitZAInstr(SMEOrigInstr, AArch64::ZAS0, MI, BB);
31423113
case (AArch64::SMEMatrixTileD):

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -653,9 +653,6 @@ class AArch64TargetLowering : public TargetLowering {
653653
MachineBasicBlock *EmitTileLoad(unsigned Opc, unsigned BaseReg,
654654
MachineInstr &MI,
655655
MachineBasicBlock *BB) const;
656-
MachineBasicBlock *EmitTileMovaz(unsigned Opc, unsigned BaseReg,
657-
MachineInstr &MI,
658-
MachineBasicBlock *BB) const;
659656
MachineBasicBlock *EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const;
660657
MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg,
661658
MachineInstr &MI, MachineBasicBlock *BB) const;

‎llvm/test/CodeGen/AArch64/sme2p1-intrinsics-movaz.ll

Lines changed: 36 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1 -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -verify-machineinstrs -force-streaming < %s | FileCheck %s
3+
4+
target triple = "aarch64-linux"
35

46
;MOVAZ (tile to vector, Multi)
57

@@ -420,7 +422,6 @@ define {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vsc
420422
ret {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>} %res
421423
}
422424

423-
attributes #0 = { "target-features"="+sve" }
424425

425426
declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.readz.horiz.za8.x2.nxv16i8(i32, i32)
426427
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.aarch64.sme.readz.horiz.x2.nxv8i16(i32, i32)
@@ -463,7 +464,7 @@ declare {<vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vs
463464
;;
464465
; Horiz
465466
;;
466-
define <vscale x 16 x i8> @test_readz_hor_z8_i8(i32 %tile, i32 %slice) {
467+
define <vscale x 16 x i8> @test_readz_hor_z8_i8(i32 %tile, i32 %slice) #0 {
467468
; CHECK-LABEL: test_readz_hor_z8_i8:
468469
; CHECK: // %bb.0:
469470
; CHECK-NEXT: mov w12, w1
@@ -476,7 +477,7 @@ define <vscale x 16 x i8> @test_readz_hor_z8_i8(i32 %tile, i32 %slice) {
476477
ret <vscale x 16 x i8> %res2
477478
}
478479

479-
define <vscale x 8 x i16> @test_readz_hor_z16_i16(i32 %tile, i32 %slice) {
480+
define <vscale x 8 x i16> @test_readz_hor_z16_i16(i32 %tile, i32 %slice) #0 {
480481
; CHECK-LABEL: test_readz_hor_z16_i16:
481482
; CHECK: // %bb.0:
482483
; CHECK-NEXT: mov w12, w1
@@ -489,7 +490,7 @@ define <vscale x 8 x i16> @test_readz_hor_z16_i16(i32 %tile, i32 %slice) {
489490
ret <vscale x 8 x i16> %res2
490491
}
491492

492-
define <vscale x 4 x i32> @test_readz_hor_z32_i32(i32 %tile, i32 %slice) {
493+
define <vscale x 4 x i32> @test_readz_hor_z32_i32(i32 %tile, i32 %slice) #0 {
493494
; CHECK-LABEL: test_readz_hor_z32_i32:
494495
; CHECK: // %bb.0:
495496
; CHECK-NEXT: mov w12, w1
@@ -502,7 +503,7 @@ define <vscale x 4 x i32> @test_readz_hor_z32_i32(i32 %tile, i32 %slice) {
502503
ret <vscale x 4 x i32> %res2
503504
}
504505

505-
define <vscale x 2 x i64> @test_readz_hor_z64_i64(i32 %tile, i32 %slice) {
506+
define <vscale x 2 x i64> @test_readz_hor_z64_i64(i32 %tile, i32 %slice) #0 {
506507
; CHECK-LABEL: test_readz_hor_z64_i64:
507508
; CHECK: // %bb.0:
508509
; CHECK-NEXT: mov w12, w1
@@ -515,7 +516,7 @@ define <vscale x 2 x i64> @test_readz_hor_z64_i64(i32 %tile, i32 %slice) {
515516
ret <vscale x 2 x i64> %res
516517
}
517518

518-
define <vscale x 8 x bfloat> @test_readz_hor_z16_bf16(i32 %tile, i32 %slice) {
519+
define <vscale x 8 x bfloat> @test_readz_hor_z16_bf16(i32 %tile, i32 %slice) #0 {
519520
; CHECK-LABEL: test_readz_hor_z16_bf16:
520521
; CHECK: // %bb.0:
521522
; CHECK-NEXT: mov w12, w1
@@ -528,7 +529,7 @@ define <vscale x 8 x bfloat> @test_readz_hor_z16_bf16(i32 %tile, i32 %slice) {
528529
ret <vscale x 8 x bfloat> %res2
529530
}
530531

531-
define <vscale x 8 x half> @test_readz_hor_z16_f16(i32 %tile, i32 %slice) {
532+
define <vscale x 8 x half> @test_readz_hor_z16_f16(i32 %tile, i32 %slice) #0 {
532533
; CHECK-LABEL: test_readz_hor_z16_f16:
533534
; CHECK: // %bb.0:
534535
; CHECK-NEXT: mov w12, w1
@@ -541,7 +542,7 @@ define <vscale x 8 x half> @test_readz_hor_z16_f16(i32 %tile, i32 %slice) {
541542
ret <vscale x 8 x half> %res2
542543
}
543544

544-
define <vscale x 4 x float> @test_readz_hor_z32_f32(i32 %tile, i32 %slice) {
545+
define <vscale x 4 x float> @test_readz_hor_z32_f32(i32 %tile, i32 %slice) #0 {
545546
; CHECK-LABEL: test_readz_hor_z32_f32:
546547
; CHECK: // %bb.0:
547548
; CHECK-NEXT: mov w12, w1
@@ -554,7 +555,7 @@ define <vscale x 4 x float> @test_readz_hor_z32_f32(i32 %tile, i32 %slice) {
554555
ret <vscale x 4 x float> %res2
555556
}
556557

557-
define <vscale x 2 x double> @test_readz_hor_z64_f64(i32 %tile, i32 %slice) {
558+
define <vscale x 2 x double> @test_readz_hor_z64_f64(i32 %tile, i32 %slice) #0 {
558559
; CHECK-LABEL: test_readz_hor_z64_f64:
559560
; CHECK: // %bb.0:
560561
; CHECK-NEXT: mov w12, w1
@@ -567,7 +568,7 @@ define <vscale x 2 x double> @test_readz_hor_z64_f64(i32 %tile, i32 %slice) {
567568
ret <vscale x 2 x double> %res
568569
}
569570

570-
define <vscale x 16 x i8> @test_readz_hor_z128_i8(i32 %tile, i32 %slice) {
571+
define <vscale x 16 x i8> @test_readz_hor_z128_i8(i32 %tile, i32 %slice) #0 {
571572
; CHECK-LABEL: test_readz_hor_z128_i8:
572573
; CHECK: // %bb.0:
573574
; CHECK-NEXT: mov w12, w1
@@ -579,7 +580,7 @@ define <vscale x 16 x i8> @test_readz_hor_z128_i8(i32 %tile, i32 %slice) {
579580
ret <vscale x 16 x i8> %res2
580581
}
581582

582-
define <vscale x 8 x i16> @test_readz_hor_z128_i16(i32 %tile, i32 %slice) {
583+
define <vscale x 8 x i16> @test_readz_hor_z128_i16(i32 %tile, i32 %slice) #0 {
583584
; CHECK-LABEL: test_readz_hor_z128_i16:
584585
; CHECK: // %bb.0:
585586
; CHECK-NEXT: mov w12, w1
@@ -591,7 +592,7 @@ define <vscale x 8 x i16> @test_readz_hor_z128_i16(i32 %tile, i32 %slice) {
591592
ret <vscale x 8 x i16> %res2
592593
}
593594

594-
define <vscale x 4 x i32> @test_readz_hor_z128_i32(i32 %tile, i32 %slice) {
595+
define <vscale x 4 x i32> @test_readz_hor_z128_i32(i32 %tile, i32 %slice) #0 {
595596
; CHECK-LABEL: test_readz_hor_z128_i32:
596597
; CHECK: // %bb.0:
597598
; CHECK-NEXT: mov w12, w1
@@ -603,7 +604,7 @@ define <vscale x 4 x i32> @test_readz_hor_z128_i32(i32 %tile, i32 %slice) {
603604
ret <vscale x 4 x i32> %res2
604605
}
605606

606-
define <vscale x 2 x i64> @test_readz_hor_z128_i64(i32 %tile, i32 %slice) {
607+
define <vscale x 2 x i64> @test_readz_hor_z128_i64(i32 %tile, i32 %slice) #0 {
607608
; CHECK-LABEL: test_readz_hor_z128_i64:
608609
; CHECK: // %bb.0:
609610
; CHECK-NEXT: mov w12, w1
@@ -615,7 +616,7 @@ define <vscale x 2 x i64> @test_readz_hor_z128_i64(i32 %tile, i32 %slice) {
615616
ret <vscale x 2 x i64> %res
616617
}
617618

618-
define <vscale x 8 x bfloat> @test_readz_hor_z128_bf16(i32 %tile, i32 %slice) {
619+
define <vscale x 8 x bfloat> @test_readz_hor_z128_bf16(i32 %tile, i32 %slice) #0 {
619620
; CHECK-LABEL: test_readz_hor_z128_bf16:
620621
; CHECK: // %bb.0:
621622
; CHECK-NEXT: mov w12, w1
@@ -627,7 +628,7 @@ define <vscale x 8 x bfloat> @test_readz_hor_z128_bf16(i32 %tile, i32 %slice) {
627628
ret <vscale x 8 x bfloat> %res2
628629
}
629630

630-
define <vscale x 8 x half> @test_readz_hor_z128_f16(i32 %tile, i32 %slice) {
631+
define <vscale x 8 x half> @test_readz_hor_z128_f16(i32 %tile, i32 %slice) #0 {
631632
; CHECK-LABEL: test_readz_hor_z128_f16:
632633
; CHECK: // %bb.0:
633634
; CHECK-NEXT: mov w12, w1
@@ -639,7 +640,7 @@ define <vscale x 8 x half> @test_readz_hor_z128_f16(i32 %tile, i32 %slice) {
639640
ret <vscale x 8 x half> %res2
640641
}
641642

642-
define <vscale x 4 x float> @test_readz_hor_z128_f32(i32 %tile, i32 %slice) {
643+
define <vscale x 4 x float> @test_readz_hor_z128_f32(i32 %tile, i32 %slice) #0 {
643644
; CHECK-LABEL: test_readz_hor_z128_f32:
644645
; CHECK: // %bb.0:
645646
; CHECK-NEXT: mov w12, w1
@@ -651,7 +652,7 @@ define <vscale x 4 x float> @test_readz_hor_z128_f32(i32 %tile, i32 %slice) {
651652
ret <vscale x 4 x float> %res2
652653
}
653654

654-
define <vscale x 2 x double> @test_readz_hor_z128_f64(i32 %tile, i32 %slice) {
655+
define <vscale x 2 x double> @test_readz_hor_z128_f64(i32 %tile, i32 %slice) #0 {
655656
; CHECK-LABEL: test_readz_hor_z128_f64:
656657
; CHECK: // %bb.0:
657658
; CHECK-NEXT: mov w12, w1
@@ -666,7 +667,7 @@ define <vscale x 2 x double> @test_readz_hor_z128_f64(i32 %tile, i32 %slice) {
666667
;;
667668
; Vert
668669
;;
669-
define <vscale x 16 x i8> @test_readz_ver_z8_i8(i32 %tile, i32 %slice) {
670+
define <vscale x 16 x i8> @test_readz_ver_z8_i8(i32 %tile, i32 %slice) #0 {
670671
; CHECK-LABEL: test_readz_ver_z8_i8:
671672
; CHECK: // %bb.0:
672673
; CHECK-NEXT: mov w12, w1
@@ -679,7 +680,7 @@ define <vscale x 16 x i8> @test_readz_ver_z8_i8(i32 %tile, i32 %slice) {
679680
ret <vscale x 16 x i8> %res2
680681
}
681682

682-
define <vscale x 8 x i16> @test_readz_ver_z16_i16(i32 %tile, i32 %slice) {
683+
define <vscale x 8 x i16> @test_readz_ver_z16_i16(i32 %tile, i32 %slice) #0 {
683684
; CHECK-LABEL: test_readz_ver_z16_i16:
684685
; CHECK: // %bb.0:
685686
; CHECK-NEXT: mov w12, w1
@@ -692,7 +693,7 @@ define <vscale x 8 x i16> @test_readz_ver_z16_i16(i32 %tile, i32 %slice) {
692693
ret <vscale x 8 x i16> %res2
693694
}
694695

695-
define <vscale x 4 x i32> @test_readz_ver_z32_i32(i32 %tile, i32 %slice) {
696+
define <vscale x 4 x i32> @test_readz_ver_z32_i32(i32 %tile, i32 %slice) #0 {
696697
; CHECK-LABEL: test_readz_ver_z32_i32:
697698
; CHECK: // %bb.0:
698699
; CHECK-NEXT: mov w12, w1
@@ -705,7 +706,7 @@ define <vscale x 4 x i32> @test_readz_ver_z32_i32(i32 %tile, i32 %slice) {
705706
ret <vscale x 4 x i32> %res2
706707
}
707708

708-
define <vscale x 2 x i64> @test_readz_ver_z64_i64(i32 %tile, i32 %slice) {
709+
define <vscale x 2 x i64> @test_readz_ver_z64_i64(i32 %tile, i32 %slice) #0 {
709710
; CHECK-LABEL: test_readz_ver_z64_i64:
710711
; CHECK: // %bb.0:
711712
; CHECK-NEXT: mov w12, w1
@@ -718,7 +719,7 @@ define <vscale x 2 x i64> @test_readz_ver_z64_i64(i32 %tile, i32 %slice) {
718719
ret <vscale x 2 x i64> %res
719720
}
720721

721-
define <vscale x 8 x bfloat> @test_readz_ver_z16_bf16(i32 %tile, i32 %slice) {
722+
define <vscale x 8 x bfloat> @test_readz_ver_z16_bf16(i32 %tile, i32 %slice) #0 {
722723
; CHECK-LABEL: test_readz_ver_z16_bf16:
723724
; CHECK: // %bb.0:
724725
; CHECK-NEXT: mov w12, w1
@@ -731,7 +732,7 @@ define <vscale x 8 x bfloat> @test_readz_ver_z16_bf16(i32 %tile, i32 %slice) {
731732
ret <vscale x 8 x bfloat> %res2
732733
}
733734

734-
define <vscale x 8 x half> @test_readz_ver_z16_f16(i32 %tile, i32 %slice) {
735+
define <vscale x 8 x half> @test_readz_ver_z16_f16(i32 %tile, i32 %slice) #0 {
735736
; CHECK-LABEL: test_readz_ver_z16_f16:
736737
; CHECK: // %bb.0:
737738
; CHECK-NEXT: mov w12, w1
@@ -744,7 +745,7 @@ define <vscale x 8 x half> @test_readz_ver_z16_f16(i32 %tile, i32 %slice) {
744745
ret <vscale x 8 x half> %res2
745746
}
746747

747-
define <vscale x 4 x float> @test_readz_ver_z32_f32(i32 %tile, i32 %slice) {
748+
define <vscale x 4 x float> @test_readz_ver_z32_f32(i32 %tile, i32 %slice) #0 {
748749
; CHECK-LABEL: test_readz_ver_z32_f32:
749750
; CHECK: // %bb.0:
750751
; CHECK-NEXT: mov w12, w1
@@ -757,7 +758,7 @@ define <vscale x 4 x float> @test_readz_ver_z32_f32(i32 %tile, i32 %slice) {
757758
ret <vscale x 4 x float> %res2
758759
}
759760

760-
define <vscale x 2 x double> @test_readz_ver_z64_f64(i32 %tile, i32 %slice) {
761+
define <vscale x 2 x double> @test_readz_ver_z64_f64(i32 %tile, i32 %slice) #0 {
761762
; CHECK-LABEL: test_readz_ver_z64_f64:
762763
; CHECK: // %bb.0:
763764
; CHECK-NEXT: mov w12, w1
@@ -770,7 +771,7 @@ define <vscale x 2 x double> @test_readz_ver_z64_f64(i32 %tile, i32 %slice) {
770771
ret <vscale x 2 x double> %res
771772
}
772773

773-
define <vscale x 16 x i8> @test_readz_ver_z128_i8(i32 %tile, i32 %slice) {
774+
define <vscale x 16 x i8> @test_readz_ver_z128_i8(i32 %tile, i32 %slice) #0 {
774775
; CHECK-LABEL: test_readz_ver_z128_i8:
775776
; CHECK: // %bb.0:
776777
; CHECK-NEXT: mov w12, w1
@@ -782,7 +783,7 @@ define <vscale x 16 x i8> @test_readz_ver_z128_i8(i32 %tile, i32 %slice) {
782783
ret <vscale x 16 x i8> %res2
783784
}
784785

785-
define <vscale x 8 x i16> @test_readz_ver_z128_i16(i32 %tile, i32 %slice) {
786+
define <vscale x 8 x i16> @test_readz_ver_z128_i16(i32 %tile, i32 %slice) #0 {
786787
; CHECK-LABEL: test_readz_ver_z128_i16:
787788
; CHECK: // %bb.0:
788789
; CHECK-NEXT: mov w12, w1
@@ -794,7 +795,7 @@ define <vscale x 8 x i16> @test_readz_ver_z128_i16(i32 %tile, i32 %slice) {
794795
ret <vscale x 8 x i16> %res2
795796
}
796797

797-
define <vscale x 4 x i32> @test_readz_ver_z128_i32(i32 %tile, i32 %slice) {
798+
define <vscale x 4 x i32> @test_readz_ver_z128_i32(i32 %tile, i32 %slice) #0 {
798799
; CHECK-LABEL: test_readz_ver_z128_i32:
799800
; CHECK: // %bb.0:
800801
; CHECK-NEXT: mov w12, w1
@@ -806,7 +807,7 @@ define <vscale x 4 x i32> @test_readz_ver_z128_i32(i32 %tile, i32 %slice) {
806807
ret <vscale x 4 x i32> %res2
807808
}
808809

809-
define <vscale x 2 x i64> @test_readz_ver_z128_i64(i32 %tile, i32 %slice) {
810+
define <vscale x 2 x i64> @test_readz_ver_z128_i64(i32 %tile, i32 %slice) #0 {
810811
; CHECK-LABEL: test_readz_ver_z128_i64:
811812
; CHECK: // %bb.0:
812813
; CHECK-NEXT: mov w12, w1
@@ -818,7 +819,7 @@ define <vscale x 2 x i64> @test_readz_ver_z128_i64(i32 %tile, i32 %slice) {
818819
ret <vscale x 2 x i64> %res
819820
}
820821

821-
define <vscale x 8 x bfloat> @test_readz_ver_z128_bf16(i32 %tile, i32 %slice) {
822+
define <vscale x 8 x bfloat> @test_readz_ver_z128_bf16(i32 %tile, i32 %slice) #0 {
822823
; CHECK-LABEL: test_readz_ver_z128_bf16:
823824
; CHECK: // %bb.0:
824825
; CHECK-NEXT: mov w12, w1
@@ -830,7 +831,7 @@ define <vscale x 8 x bfloat> @test_readz_ver_z128_bf16(i32 %tile, i32 %slice) {
830831
ret <vscale x 8 x bfloat> %res2
831832
}
832833

833-
define <vscale x 8 x half> @test_readz_ver_z128_f16(i32 %tile, i32 %slice) {
834+
define <vscale x 8 x half> @test_readz_ver_z128_f16(i32 %tile, i32 %slice) #0 {
834835
; CHECK-LABEL: test_readz_ver_z128_f16:
835836
; CHECK: // %bb.0:
836837
; CHECK-NEXT: mov w12, w1
@@ -842,7 +843,7 @@ define <vscale x 8 x half> @test_readz_ver_z128_f16(i32 %tile, i32 %slice) {
842843
ret <vscale x 8 x half> %res2
843844
}
844845

845-
define <vscale x 4 x float> @test_readz_ver_z128_f32(i32 %tile, i32 %slice) {
846+
define <vscale x 4 x float> @test_readz_ver_z128_f32(i32 %tile, i32 %slice) #0 {
846847
; CHECK-LABEL: test_readz_ver_z128_f32:
847848
; CHECK: // %bb.0:
848849
; CHECK-NEXT: mov w12, w1
@@ -854,7 +855,7 @@ define <vscale x 4 x float> @test_readz_ver_z128_f32(i32 %tile, i32 %slice) {
854855
ret <vscale x 4 x float> %res2
855856
}
856857

857-
define <vscale x 2 x double> @test_readz_ver_z128_f64(i32 %tile, i32 %slice) {
858+
define <vscale x 2 x double> @test_readz_ver_z128_f64(i32 %tile, i32 %slice) #0 {
858859
; CHECK-LABEL: test_readz_ver_z128_f64:
859860
; CHECK: // %bb.0:
860861
; CHECK-NEXT: mov w12, w1
@@ -900,3 +901,4 @@ declare <vscale x 8 x bfloat> @llvm.aarch64.sme.readz.q.vert.nxv8bf16(i32, i32)
900901
declare <vscale x 8 x half> @llvm.aarch64.sme.readz.q.vert.nxv8f16(i32, i32)
901902
declare <vscale x 4 x float> @llvm.aarch64.sme.readz.q.vert.nxv4f32(i32, i32)
902903
declare <vscale x 2 x double> @llvm.aarch64.sme.readz.q.vert.nxv2f64(i32, i32)
904+
attributes #0 = { nounwind "target-features" = "+sme2p1"}

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