Skip to content

Commit 9030e7d

Browse files
davemgreendavemgreen
committed
[AArch64] Add tests for reassociating to mls. NFC
1 parent 9225d08 commit 9030e7d

File tree

1 file changed

+234
-0
lines changed

1 file changed

+234
-0
lines changed

‎llvm/test/CodeGen/AArch64/reassocmls.ll

Lines changed: 234 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,234 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+sve2 | FileCheck %s
3+
4+
define i64 @smlsl_i64(i64 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
5+
; CHECK-LABEL: smlsl_i64:
6+
; CHECK: // %bb.0:
7+
; CHECK-NEXT: smull x8, w4, w3
8+
; CHECK-NEXT: smaddl x8, w2, w1, x8
9+
; CHECK-NEXT: sub x0, x0, x8
10+
; CHECK-NEXT: ret
11+
%be = sext i32 %b to i64
12+
%ce = sext i32 %c to i64
13+
%de = sext i32 %d to i64
14+
%ee = sext i32 %e to i64
15+
%m1.neg = mul nsw i64 %ce, %be
16+
%m2.neg = mul nsw i64 %ee, %de
17+
%reass.add = add i64 %m2.neg, %m1.neg
18+
%s2 = sub i64 %a, %reass.add
19+
ret i64 %s2
20+
}
21+
22+
define i64 @umlsl_i64(i64 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
23+
; CHECK-LABEL: umlsl_i64:
24+
; CHECK: // %bb.0:
25+
; CHECK-NEXT: umull x8, w4, w3
26+
; CHECK-NEXT: umaddl x8, w2, w1, x8
27+
; CHECK-NEXT: sub x0, x0, x8
28+
; CHECK-NEXT: ret
29+
%be = zext i32 %b to i64
30+
%ce = zext i32 %c to i64
31+
%de = zext i32 %d to i64
32+
%ee = zext i32 %e to i64
33+
%m1.neg = mul nuw i64 %ce, %be
34+
%m2.neg = mul nuw i64 %ee, %de
35+
%reass.add = add i64 %m2.neg, %m1.neg
36+
%s2 = sub i64 %a, %reass.add
37+
ret i64 %s2
38+
}
39+
40+
define i64 @mls_i64(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {
41+
; CHECK-LABEL: mls_i64:
42+
; CHECK: // %bb.0:
43+
; CHECK-NEXT: mul x8, x2, x1
44+
; CHECK-NEXT: madd x8, x4, x3, x8
45+
; CHECK-NEXT: sub x0, x0, x8
46+
; CHECK-NEXT: ret
47+
%m1.neg = mul i64 %c, %b
48+
%m2.neg = mul i64 %e, %d
49+
%reass.add = add i64 %m2.neg, %m1.neg
50+
%s2 = sub i64 %a, %reass.add
51+
ret i64 %s2
52+
}
53+
54+
define i16 @mls_i16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e) {
55+
; CHECK-LABEL: mls_i16:
56+
; CHECK: // %bb.0:
57+
; CHECK-NEXT: mul w8, w2, w1
58+
; CHECK-NEXT: madd w8, w4, w3, w8
59+
; CHECK-NEXT: sub w0, w0, w8
60+
; CHECK-NEXT: ret
61+
%m1.neg = mul i16 %c, %b
62+
%m2.neg = mul i16 %e, %d
63+
%reass.add = add i16 %m2.neg, %m1.neg
64+
%s2 = sub i16 %a, %reass.add
65+
ret i16 %s2
66+
}
67+
68+
define i64 @mla_i64(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {
69+
; CHECK-LABEL: mla_i64:
70+
; CHECK: // %bb.0:
71+
; CHECK-NEXT: madd x8, x2, x1, x0
72+
; CHECK-NEXT: madd x0, x4, x3, x8
73+
; CHECK-NEXT: ret
74+
%m1 = mul i64 %c, %b
75+
%m2 = mul i64 %e, %d
76+
%s1 = add i64 %m1, %a
77+
%s2 = add i64 %s1, %m2
78+
ret i64 %s2
79+
}
80+
81+
define i64 @mls_i64_C(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {
82+
; CHECK-LABEL: mls_i64_C:
83+
; CHECK: // %bb.0:
84+
; CHECK-NEXT: mul x8, x2, x1
85+
; CHECK-NEXT: mov w9, #10
86+
; CHECK-NEXT: madd x8, x4, x3, x8
87+
; CHECK-NEXT: sub x0, x9, x8
88+
; CHECK-NEXT: ret
89+
%m1.neg = mul i64 %c, %b
90+
%m2.neg = mul i64 %e, %d
91+
%reass.add = add i64 %m2.neg, %m1.neg
92+
%s2 = sub i64 10, %reass.add
93+
ret i64 %s2
94+
}
95+
96+
97+
define <8 x i16> @smlsl_v8i16(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d, <8 x i8> %e) {
98+
; CHECK-LABEL: smlsl_v8i16:
99+
; CHECK: // %bb.0:
100+
; CHECK-NEXT: smull v3.8h, v4.8b, v3.8b
101+
; CHECK-NEXT: smlal v3.8h, v2.8b, v1.8b
102+
; CHECK-NEXT: sub v0.8h, v0.8h, v3.8h
103+
; CHECK-NEXT: ret
104+
%be = sext <8 x i8> %b to <8 x i16>
105+
%ce = sext <8 x i8> %c to <8 x i16>
106+
%de = sext <8 x i8> %d to <8 x i16>
107+
%ee = sext <8 x i8> %e to <8 x i16>
108+
%m1.neg = mul nsw <8 x i16> %ce, %be
109+
%m2.neg = mul nsw <8 x i16> %ee, %de
110+
%reass.add = add <8 x i16> %m2.neg, %m1.neg
111+
%s2 = sub <8 x i16> %a, %reass.add
112+
ret <8 x i16> %s2
113+
}
114+
115+
define <8 x i16> @umlsl_v8i16(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d, <8 x i8> %e) {
116+
; CHECK-LABEL: umlsl_v8i16:
117+
; CHECK: // %bb.0:
118+
; CHECK-NEXT: umull v3.8h, v4.8b, v3.8b
119+
; CHECK-NEXT: umlal v3.8h, v2.8b, v1.8b
120+
; CHECK-NEXT: sub v0.8h, v0.8h, v3.8h
121+
; CHECK-NEXT: ret
122+
%be = zext <8 x i8> %b to <8 x i16>
123+
%ce = zext <8 x i8> %c to <8 x i16>
124+
%de = zext <8 x i8> %d to <8 x i16>
125+
%ee = zext <8 x i8> %e to <8 x i16>
126+
%m1.neg = mul nuw <8 x i16> %ce, %be
127+
%m2.neg = mul nuw <8 x i16> %ee, %de
128+
%reass.add = add <8 x i16> %m2.neg, %m1.neg
129+
%s2 = sub <8 x i16> %a, %reass.add
130+
ret <8 x i16> %s2
131+
}
132+
133+
define <8 x i16> @mls_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e) {
134+
; CHECK-LABEL: mls_v8i16:
135+
; CHECK: // %bb.0:
136+
; CHECK-NEXT: mul v1.8h, v2.8h, v1.8h
137+
; CHECK-NEXT: mla v1.8h, v4.8h, v3.8h
138+
; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h
139+
; CHECK-NEXT: ret
140+
%m1.neg = mul <8 x i16> %c, %b
141+
%m2.neg = mul <8 x i16> %e, %d
142+
%reass.add = add <8 x i16> %m2.neg, %m1.neg
143+
%s2 = sub <8 x i16> %a, %reass.add
144+
ret <8 x i16> %s2
145+
}
146+
147+
define <8 x i16> @mla_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e) {
148+
; CHECK-LABEL: mla_v8i16:
149+
; CHECK: // %bb.0:
150+
; CHECK-NEXT: mla v0.8h, v2.8h, v1.8h
151+
; CHECK-NEXT: mla v0.8h, v4.8h, v3.8h
152+
; CHECK-NEXT: ret
153+
%m1 = mul <8 x i16> %c, %b
154+
%m2 = mul <8 x i16> %e, %d
155+
%s1 = add <8 x i16> %m1, %a
156+
%s2 = add <8 x i16> %s1, %m2
157+
ret <8 x i16> %s2
158+
}
159+
160+
161+
define <vscale x 8 x i16> @smlsl_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e) {
162+
; CHECK-LABEL: smlsl_nxv8i16:
163+
; CHECK: // %bb.0:
164+
; CHECK-NEXT: ptrue p0.h
165+
; CHECK-NEXT: sxtb z3.h, p0/m, z3.h
166+
; CHECK-NEXT: sxtb z4.h, p0/m, z4.h
167+
; CHECK-NEXT: sxtb z1.h, p0/m, z1.h
168+
; CHECK-NEXT: sxtb z2.h, p0/m, z2.h
169+
; CHECK-NEXT: mul z3.h, z4.h, z3.h
170+
; CHECK-NEXT: mla z3.h, p0/m, z2.h, z1.h
171+
; CHECK-NEXT: sub z0.h, z0.h, z3.h
172+
; CHECK-NEXT: ret
173+
%be = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>
174+
%ce = sext <vscale x 8 x i8> %c to <vscale x 8 x i16>
175+
%de = sext <vscale x 8 x i8> %d to <vscale x 8 x i16>
176+
%ee = sext <vscale x 8 x i8> %e to <vscale x 8 x i16>
177+
%m1.neg = mul nsw <vscale x 8 x i16> %ce, %be
178+
%m2.neg = mul nsw <vscale x 8 x i16> %ee, %de
179+
%reass.add = add <vscale x 8 x i16> %m2.neg, %m1.neg
180+
%s2 = sub <vscale x 8 x i16> %a, %reass.add
181+
ret <vscale x 8 x i16> %s2
182+
}
183+
184+
define <vscale x 8 x i16> @umlsl_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e) {
185+
; CHECK-LABEL: umlsl_nxv8i16:
186+
; CHECK: // %bb.0:
187+
; CHECK-NEXT: and z3.h, z3.h, #0xff
188+
; CHECK-NEXT: and z4.h, z4.h, #0xff
189+
; CHECK-NEXT: ptrue p0.h
190+
; CHECK-NEXT: and z1.h, z1.h, #0xff
191+
; CHECK-NEXT: and z2.h, z2.h, #0xff
192+
; CHECK-NEXT: mul z3.h, z4.h, z3.h
193+
; CHECK-NEXT: mla z3.h, p0/m, z2.h, z1.h
194+
; CHECK-NEXT: sub z0.h, z0.h, z3.h
195+
; CHECK-NEXT: ret
196+
%be = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
197+
%ce = zext <vscale x 8 x i8> %c to <vscale x 8 x i16>
198+
%de = zext <vscale x 8 x i8> %d to <vscale x 8 x i16>
199+
%ee = zext <vscale x 8 x i8> %e to <vscale x 8 x i16>
200+
%m1.neg = mul nuw <vscale x 8 x i16> %ce, %be
201+
%m2.neg = mul nuw <vscale x 8 x i16> %ee, %de
202+
%reass.add = add <vscale x 8 x i16> %m2.neg, %m1.neg
203+
%s2 = sub <vscale x 8 x i16> %a, %reass.add
204+
ret <vscale x 8 x i16> %s2
205+
}
206+
207+
define <vscale x 8 x i16> @mls_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e) {
208+
; CHECK-LABEL: mls_nxv8i16:
209+
; CHECK: // %bb.0:
210+
; CHECK-NEXT: ptrue p0.h
211+
; CHECK-NEXT: mul z3.h, z4.h, z3.h
212+
; CHECK-NEXT: mla z3.h, p0/m, z2.h, z1.h
213+
; CHECK-NEXT: sub z0.h, z0.h, z3.h
214+
; CHECK-NEXT: ret
215+
%m1.neg = mul <vscale x 8 x i16> %c, %b
216+
%m2.neg = mul <vscale x 8 x i16> %e, %d
217+
%reass.add = add <vscale x 8 x i16> %m2.neg, %m1.neg
218+
%s2 = sub <vscale x 8 x i16> %a, %reass.add
219+
ret <vscale x 8 x i16> %s2
220+
}
221+
222+
define <vscale x 8 x i16> @mla_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e) {
223+
; CHECK-LABEL: mla_nxv8i16:
224+
; CHECK: // %bb.0:
225+
; CHECK-NEXT: ptrue p0.h
226+
; CHECK-NEXT: mla z0.h, p0/m, z2.h, z1.h
227+
; CHECK-NEXT: mla z0.h, p0/m, z4.h, z3.h
228+
; CHECK-NEXT: ret
229+
%m1 = mul <vscale x 8 x i16> %c, %b
230+
%m2 = mul <vscale x 8 x i16> %e, %d
231+
%s1 = add <vscale x 8 x i16> %m1, %a
232+
%s2 = add <vscale x 8 x i16> %s1, %m2
233+
ret <vscale x 8 x i16> %s2
234+
}

0 commit comments

Comments
 (0)