self review:

    - add support for selecting a non-side effect convergent intrinsic
    - update test case to not be optimized away

Author: inbelic

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -431,6 +431,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
 
   case TargetOpcode::G_INTRINSIC:
   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+  case TargetOpcode::G_INTRINSIC_CONVERGENT:
   case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS:
     return selectIntrinsic(ResVReg, ResType, I);
   case TargetOpcode::G_BITREVERSE:

llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveReadLaneAt.ll

@@ -1,27 +1,39 @@
 ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32v1.3-vulkan-unknown %s -o - | FileCheck %s
 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
 
-; Test lowering to spir-v backend
+; Test lowering to spir-v backend for various types and scalar/vector
 
-; CHECK-DAG:   %[[#uint:]] = OpTypeInt 32 0
-; CHECK-DAG:   %[[#scope:]] = OpConstant %[[#uint]] 3
 ; CHECK-DAG:   %[[#f32:]] = OpTypeFloat 32
+; CHECK-DAG:   %[[#uint:]] = OpTypeInt 32 0
 ; CHECK-DAG:   %[[#bool:]] = OpTypeBool
 ; CHECK-DAG:   %[[#v4_bool:]] = OpTypeVector %[[#bool]] 4
-; CHECK-DAG:   %[[#fexpr:]] = OpFunctionParameter %[[#f32]]
-; CHECK-DAG:   %[[#iexpr:]] = OpFunctionParameter %[[#uint]]
-; CHECK-DAG:   %[[#idx:]] = OpFunctionParameter %[[#uint]]
-; CHECK-DAG:   %[[#vbexpr:]] = OpFunctionParameter %[[#v4_bool]]
+; CHECK-DAG:   %[[#scope:]] = OpConstant %[[#uint]] 3
 
-define spir_func void @test_1(float %fexpr, i32 %iexpr, <4 x i1> %vbexpr, i32 %idx) {
+; CHECK:   %[[#fexpr:]] = OpFunctionParameter %[[#f32]]
+; CHECK:   %[[#idx1:]] = OpFunctionParameter %[[#uint]]
+define float @test_1(float %fexpr, i32 %idx) {
 entry:
-; CHECK:   %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#fexpr]] %[[#idx]] %[[#scope]]
+; CHECK:   %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#fexpr]] %[[#idx1]] %[[#scope]]
   %0 = call float @llvm.spv.waveReadLaneAt.f32(float %fexpr, i32 %idx)
-; CHECK:   %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#iexpr]] %[[#idx]] %[[#scope]]
-  %1 = call i32 @llvm.spv.waveReadLaneAt.i32(i32 %iexpr, i32 %idx)
-; CHECK:   %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#vbexpr]] %[[#idx]] %[[#scope]]
-  %2 = call <4 x i1> @llvm.spv.waveReadLaneAt.v4i1(<4 x i1> %vbexpr, i32 %idx)
-  ret void
+  ret float %0
+}
+
+; CHECK:   %[[#iexpr:]] = OpFunctionParameter %[[#uint]]
+; CHECK:   %[[#idx2:]] = OpFunctionParameter %[[#uint]]
+define i32 @test_2(i32 %iexpr, i32 %idx) {
+entry:
+; CHECK:   %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#iexpr]] %[[#idx2]] %[[#scope]]
+  %0 = call i32 @llvm.spv.waveReadLaneAt.i32(i32 %iexpr, i32 %idx)
+  ret i32 %0
+}
+
+; CHECK:   %[[#vbexpr:]] = OpFunctionParameter %[[#v4_bool]]
+; CHECK:   %[[#idx3:]] = OpFunctionParameter %[[#uint]]
+define <4 x i1> @test_3(<4 x i1> %vbexpr, i32 %idx) {
+entry:
+; CHECK:   %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#vbexpr]] %[[#idx3]] %[[#scope]]
+  %0 = call <4 x i1> @llvm.spv.waveReadLaneAt.v4i1(<4 x i1> %vbexpr, i32 %idx)
+  ret <4 x i1> %0
 }
 
 declare float @llvm.spv.waveReadLaneAt.f32(float, i32)