|
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt -passes=instcombine -S < %s | FileCheck %s |
| 3 | + |
| 4 | +; Tests for select to scmp |
| 5 | + |
| 6 | +define i32 @scmp_x_0_inverted(i32 %x) { |
| 7 | +; CHECK-LABEL: define i32 @scmp_x_0_inverted( |
| 8 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 9 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[X]], 0 |
| 10 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32 |
| 11 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], -1 |
| 12 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1 |
| 13 | +; CHECK-NEXT: ret i32 [[TMP1]] |
| 14 | +; |
| 15 | + %2 = icmp ne i32 %x, 0 |
| 16 | + %3 = zext i1 %2 to i32 |
| 17 | + %4 = icmp sgt i32 %x, -1 |
| 18 | + %5 = select i1 %4, i32 %3, i32 -1 |
| 19 | + ret i32 %5 |
| 20 | +} |
| 21 | + |
| 22 | +; y = -10 |
| 23 | +define i32 @scmp_x_0_inverted_const_neg10(i32 %x) { |
| 24 | +; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_neg10( |
| 25 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 26 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[X]], -10 |
| 27 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32 |
| 28 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], -11 |
| 29 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1 |
| 30 | +; CHECK-NEXT: ret i32 [[TMP1]] |
| 31 | +; |
| 32 | + %1 = icmp ne i32 %x, -10 |
| 33 | + %2 = zext i1 %1 to i32 |
| 34 | + %3 = icmp sgt i32 %x, -11 |
| 35 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 36 | + ret i32 %4 |
| 37 | +} |
| 38 | + |
| 39 | +; y = 7 (i8) |
| 40 | +define i8 @scmp_x_0_inverted_i8(i8 %x) { |
| 41 | +; CHECK-LABEL: define i8 @scmp_x_0_inverted_i8( |
| 42 | +; CHECK-SAME: i8 [[X:%.*]]) { |
| 43 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i8 [[X]], 7 |
| 44 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i8 |
| 45 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i8 [[X]], 6 |
| 46 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i8 [[TMP2]], i8 -1 |
| 47 | +; CHECK-NEXT: ret i8 [[TMP1]] |
| 48 | +; |
| 49 | + %1 = icmp ne i8 %x, 7 |
| 50 | + %2 = zext i1 %1 to i8 |
| 51 | + %3 = icmp sgt i8 %x, 6 |
| 52 | + %4 = select i1 %3, i8 %2, i8 -1 |
| 53 | + ret i8 %4 |
| 54 | +} |
| 55 | + |
| 56 | +; scmp using ints of two kinds- i32 and i64 |
| 57 | +define i32 @scmp_x_0_inverted_i64_neq(i32 %x) { |
| 58 | +; CHECK-LABEL: define i32 @scmp_x_0_inverted_i64_neq( |
| 59 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 60 | +; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[X]], 0 |
| 61 | +; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[X]], -1 |
| 62 | +; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[CMP1]] to i32 |
| 63 | +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP2]], i32 [[TMP1]], i32 -1 |
| 64 | +; CHECK-NEXT: ret i32 [[RET]] |
| 65 | +; |
| 66 | + %x64 = sext i32 %x to i64 |
| 67 | + %cmp1 = icmp ne i64 %x64, 0 |
| 68 | + %zext = zext i1 %cmp1 to i64 |
| 69 | + %cmp2 = icmp sgt i64 %x64, -1 |
| 70 | + %sel = select i1 %cmp2, i64 %zext, i64 -1 |
| 71 | + %ret = trunc i64 %sel to i32 |
| 72 | + ret i32 %ret |
| 73 | +} |
| 74 | + |
| 75 | +; Same example as previous but with inequality |
| 76 | +define i32 @scmp_x_0_inverted_i64_sgt(i32 %x) { |
| 77 | +; CHECK-LABEL: define i32 @scmp_x_0_inverted_i64_sgt( |
| 78 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 79 | +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[X]], 0 |
| 80 | +; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[X]], -1 |
| 81 | +; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[CMP1]] to i32 |
| 82 | +; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP2]], i32 [[TMP1]], i32 -1 |
| 83 | +; CHECK-NEXT: ret i32 [[RET]] |
| 84 | +; |
| 85 | + %x64 = sext i32 %x to i64 |
| 86 | + %cmp1 = icmp sgt i64 %x64, 0 |
| 87 | + %zext = zext i1 %cmp1 to i64 |
| 88 | + %cmp2 = icmp sgt i64 %x64, -1 |
| 89 | + %sel = select i1 %cmp2, i64 %zext, i64 -1 |
| 90 | + %ret = trunc i64 %sel to i32 |
| 91 | + ret i32 %ret |
| 92 | +} |
| 93 | + |
| 94 | +; y = -1000 |
| 95 | +define i32 @scmp_x_0_inverted_const_neg1000(i32 %x) { |
| 96 | +; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_neg1000( |
| 97 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 98 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[X]], -1000 |
| 99 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32 |
| 100 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], -1001 |
| 101 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1 |
| 102 | +; CHECK-NEXT: ret i32 [[TMP1]] |
| 103 | +; |
| 104 | + %1 = icmp sgt i32 %x, -1000 |
| 105 | + %2 = zext i1 %1 to i32 |
| 106 | + %3 = icmp sgt i32 %x, -1001 |
| 107 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 108 | + ret i32 %4 |
| 109 | +} |
| 110 | + |
| 111 | +; y = 1729 |
| 112 | +define i32 @scmp_x_0_inverted_const_1729_sgt(i32 %x) { |
| 113 | +; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_1729_sgt( |
| 114 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 115 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[X]], 1729 |
| 116 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32 |
| 117 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], 1728 |
| 118 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1 |
| 119 | +; CHECK-NEXT: ret i32 [[TMP1]] |
| 120 | +; |
| 121 | + %1 = icmp sgt i32 %x, 1729 |
| 122 | + %2 = zext i1 %1 to i32 |
| 123 | + %3 = icmp sgt i32 %x, 1728 |
| 124 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 125 | + ret i32 %4 |
| 126 | +} |
| 127 | + |
| 128 | +; ucmp with 10 |
| 129 | +define i32 @ucmp_x_10_inverted(i32 %x) { |
| 130 | +; CHECK-LABEL: define i32 @ucmp_x_10_inverted( |
| 131 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 132 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[X]], 10 |
| 133 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32 |
| 134 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[X]], 9 |
| 135 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1 |
| 136 | +; CHECK-NEXT: ret i32 [[TMP1]] |
| 137 | +; |
| 138 | + %1 = icmp ne i32 %x, 10 |
| 139 | + %2 = zext i1 %1 to i32 |
| 140 | + %3 = icmp ugt i32 %x, 9 |
| 141 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 142 | + ret i32 %4 |
| 143 | +} |
| 144 | + |
| 145 | +; ucmp with -3, wraps around |
| 146 | +define i32 @ucmp_x_neg1_inverted(i32 %x) { |
| 147 | +; CHECK-LABEL: define i32 @ucmp_x_neg1_inverted( |
| 148 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 149 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[X]], -3 |
| 150 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i32 |
| 151 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i32 [[X]], -4 |
| 152 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1 |
| 153 | +; CHECK-NEXT: ret i32 [[TMP1]] |
| 154 | +; |
| 155 | + %1 = icmp ne i32 %x, -3 |
| 156 | + %2 = zext i1 %1 to i32 |
| 157 | + %3 = icmp ugt i32 %x, -4 |
| 158 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 159 | + ret i32 %4 |
| 160 | +} |
| 161 | + |
| 162 | +; ucmp with -4, wraps around |
| 163 | +define i8 @ucmp_x_neg4_i8_ugt(i8 %x) { |
| 164 | +; CHECK-LABEL: define i8 @ucmp_x_neg4_i8_ugt( |
| 165 | +; CHECK-SAME: i8 [[X:%.*]]) { |
| 166 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp ugt i8 [[X]], -4 |
| 167 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP4]] to i8 |
| 168 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp ugt i8 [[X]], -5 |
| 169 | +; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[TMP3]], i8 [[TMP2]], i8 -1 |
| 170 | +; CHECK-NEXT: ret i8 [[TMP1]] |
| 171 | +; |
| 172 | + %1 = icmp ugt i8 %x, -4 |
| 173 | + %2 = zext i1 %1 to i8 |
| 174 | + %3 = icmp ugt i8 %x, -5 |
| 175 | + %4 = select i1 %3, i8 %2, i8 -1 |
| 176 | + ret i8 %4 |
| 177 | +} |
| 178 | + |
| 179 | +; Vector tests |
| 180 | + |
| 181 | +; Test with splat vec |
| 182 | +define <4 x i32> @scmp_x_0_inverted_splat_vec(<4 x i32> %x) { |
| 183 | +; CHECK-LABEL: define <4 x i32> @scmp_x_0_inverted_splat_vec( |
| 184 | +; CHECK-SAME: <4 x i32> [[X:%.*]]) { |
| 185 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[X]], zeroinitializer |
| 186 | +; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i32> |
| 187 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[X]], splat (i32 -1) |
| 188 | +; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP2]], <4 x i32> splat (i32 -1) |
| 189 | +; CHECK-NEXT: ret <4 x i32> [[TMP1]] |
| 190 | +; |
| 191 | + %2 = icmp ne <4 x i32> %x, zeroinitializer |
| 192 | + %3 = zext <4 x i1> %2 to <4 x i32> |
| 193 | + %4 = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> |
| 194 | + %5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> |
| 195 | + ret <4 x i32> %5 |
| 196 | +} |
| 197 | + |
| 198 | +; Test with non-splat vector and different bitwidth |
| 199 | +define <4 x i32> @non_splat_vec_scmp_diff_bitwidth(<4 x i32> %x) { |
| 200 | +; CHECK-LABEL: define <4 x i32> @non_splat_vec_scmp_diff_bitwidth( |
| 201 | +; CHECK-SAME: <4 x i32> [[X:%.*]]) { |
| 202 | +; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <4 x i32> [[X]], <i32 0, i32 1, i32 -1, i32 5> |
| 203 | +; CHECK-NEXT: [[CMP2:%.*]] = icmp slt <4 x i32> [[X]], <i32 1, i32 2, i32 0, i32 6> |
| 204 | +; CHECK-NEXT: [[TMP1:%.*]] = sext <4 x i1> [[CMP1]] to <4 x i32> |
| 205 | +; CHECK-NEXT: [[RET:%.*]] = select <4 x i1> [[CMP2]], <4 x i32> [[TMP1]], <4 x i32> splat (i32 1) |
| 206 | +; CHECK-NEXT: ret <4 x i32> [[RET]] |
| 207 | +; |
| 208 | + %x64 = sext <4 x i32> %x to <4 x i64> |
| 209 | + %cmp1 = icmp slt <4 x i64> %x64, <i64 0, i64 1, i64 -1, i64 5> |
| 210 | + %sext = sext <4 x i1> %cmp1 to <4 x i64> |
| 211 | + %cmp2 = icmp slt <4 x i64> %x64, <i64 1, i64 2, i64 0, i64 6> |
| 212 | + %sel = select <4 x i1> %cmp2, <4 x i64> %sext, <4 x i64> <i64 1, i64 1, i64 1, i64 1> |
| 213 | + %ret = trunc <4 x i64> %sel to <4 x i32> |
| 214 | + ret <4 x i32> %ret |
| 215 | +} |
| 216 | + |
| 217 | +; Negative examples |
| 218 | + |
| 219 | +; Not scmp due to wrong RHS of the predicate |
| 220 | +define i32 @scmp_ne_0(i32 %0) { |
| 221 | +; CHECK-LABEL: define i32 @scmp_ne_0( |
| 222 | +; CHECK-SAME: i32 [[TMP0:%.*]]) { |
| 223 | +; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP0]], 0 |
| 224 | +; CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32 |
| 225 | +; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| 226 | +; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i32 [[TMP3]], i32 -1 |
| 227 | +; CHECK-NEXT: ret i32 [[TMP5]] |
| 228 | +; |
| 229 | + %2 = icmp ne i32 %0, 0 |
| 230 | + %3 = zext i1 %2 to i32 |
| 231 | + %4 = icmp sgt i32 %0, 1 |
| 232 | + %5 = select i1 %4, i32 %3, i32 -1 |
| 233 | + ret i32 %5 |
| 234 | +} |
| 235 | + |
| 236 | +; y = 0 with unsigned compare but RHS wraps |
| 237 | +define i32 @ucmp_x_0_inverted(i32 %x) { |
| 238 | +; CHECK-LABEL: define i32 @ucmp_x_0_inverted( |
| 239 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 240 | +; CHECK-NEXT: ret i32 -1 |
| 241 | +; |
| 242 | + %1 = icmp ne i32 %x, 0 |
| 243 | + %2 = zext i1 %1 to i32 |
| 244 | + %3 = icmp ugt i32 %x, -1 |
| 245 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 246 | + ret i32 %4 |
| 247 | +} |
| 248 | + |
| 249 | +; Don't fold with INT32_MIN |
| 250 | +define i32 @scmp_x_0_inverted_const_min(i32 %x) { |
| 251 | +; CHECK-LABEL: define i32 @scmp_x_0_inverted_const_min( |
| 252 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 253 | +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], -2147483648 |
| 254 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32 |
| 255 | +; CHECK-NEXT: ret i32 [[TMP2]] |
| 256 | +; |
| 257 | + %1 = icmp ne i32 %x, -2147483648 |
| 258 | + %2 = zext i1 %1 to i32 |
| 259 | + %3 = icmp sge i32 %x, -2147483648 |
| 260 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 261 | + ret i32 %4 |
| 262 | +} |
| 263 | + |
| 264 | +; Unsigned cmp of zext of i32 with i64 -1 should always be -1 |
| 265 | +define i32 @ucmp_x_0_inverted_i64_ugt(i32 %x) { |
| 266 | +; CHECK-LABEL: define i32 @ucmp_x_0_inverted_i64_ugt( |
| 267 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 268 | +; CHECK-NEXT: ret i32 -1 |
| 269 | +; |
| 270 | + %x64 = zext i32 %x to i64 |
| 271 | + %cmp1 = icmp ugt i64 %x64, 0 |
| 272 | + %zext = zext i1 %cmp1 to i64 |
| 273 | + %cmp2 = icmp ugt i64 %x64, -1 |
| 274 | + %sel = select i1 %cmp2, i64 %zext, i64 -1 |
| 275 | + %ret = trunc i64 %sel to i32 |
| 276 | + ret i32 %ret |
| 277 | +} |
| 278 | + |
| 279 | +; y = 4294967295 (UINT32_MAX), simply sign extend neq |
| 280 | +define i32 @ucmp_x_const_u32max(i32 %x) { |
| 281 | +; CHECK-LABEL: define i32 @ucmp_x_const_u32max( |
| 282 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 283 | +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[X]], -1 |
| 284 | +; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[TMP1]] to i32 |
| 285 | +; CHECK-NEXT: ret i32 [[TMP2]] |
| 286 | +; |
| 287 | + %1 = icmp ugt i32 %x, 4294967295 |
| 288 | + %2 = zext i1 %1 to i32 |
| 289 | + %3 = icmp ugt i32 %x, 4294967294 |
| 290 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 291 | + ret i32 %4 |
| 292 | +} |
| 293 | + |
| 294 | +; Don't fold with different signedness |
| 295 | +define i32 @different_signedness_neg(i32 %x) { |
| 296 | +; CHECK-LABEL: define i32 @different_signedness_neg( |
| 297 | +; CHECK-SAME: i32 [[X:%.*]]) { |
| 298 | +; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[X]], -10 |
| 299 | +; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[TMP1]] to i32 |
| 300 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt i32 [[X]], -11 |
| 301 | +; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 -1 |
| 302 | +; CHECK-NEXT: ret i32 [[TMP4]] |
| 303 | +; |
| 304 | + %1 = icmp ugt i32 %x, -10 |
| 305 | + %2 = zext i1 %1 to i32 |
| 306 | + %3 = icmp sgt i32 %x, -11 |
| 307 | + %4 = select i1 %3, i32 %2, i32 -1 |
| 308 | + ret i32 %4 |
| 309 | +} |
| 310 | + |
| 311 | +; Test with wrong false value |
| 312 | +define <4 x i32> @scmp_x_0_inverted_vec(<4 x i32> %x) { |
| 313 | +; CHECK-LABEL: define <4 x i32> @scmp_x_0_inverted_vec( |
| 314 | +; CHECK-SAME: <4 x i32> [[X:%.*]]) { |
| 315 | +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[X]], zeroinitializer |
| 316 | +; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> |
| 317 | +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[X]], splat (i32 -1) |
| 318 | +; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> [[TMP2]], <4 x i32> <i32 -1, i32 -2, i32 -1, i32 -1> |
| 319 | +; CHECK-NEXT: ret <4 x i32> [[TMP4]] |
| 320 | +; |
| 321 | + %2 = icmp ne <4 x i32> %x, zeroinitializer |
| 322 | + %3 = zext <4 x i1> %2 to <4 x i32> |
| 323 | + %4 = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> |
| 324 | + %5 = select <4 x i1> %4, <4 x i32> %3, <4 x i32> <i32 -1, i32 -2, i32 -1, i32 -1> |
| 325 | + ret <4 x i32> %5 |
| 326 | +} |
0 commit comments