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[AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...
Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors. Fixes #58156. Differential Revision: https://reviews.llvm.org/D143517
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‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

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Original file line numberDiff line numberDiff line change
@@ -126,6 +126,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
126126
.legalFor({v2s64})
127127
.widenScalarToNextPow2(0)
128128
.clampScalar(0, s32, s64)
129+
.clampMaxNumElements(0, s8, 16)
130+
.clampMaxNumElements(0, s16, 8)
129131
.clampNumElements(0, v2s32, v4s32)
130132
.clampNumElements(0, v2s64, v2s64)
131133
.minScalarOrEltIf(

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,46 @@ body: |
163163
$q0 = COPY %7(<2 x s64>)
164164
$q1 = COPY %8(<2 x s64>)
165165
166+
...
167+
---
168+
name: test_vector_add_v16s16
169+
body: |
170+
bb.0.entry:
171+
; CHECK-LABEL: name: test_vector_add_v16s16
172+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
173+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
174+
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY]], [[COPY]]
175+
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[COPY1]], [[COPY1]]
176+
; CHECK-NEXT: $q0 = COPY [[ADD]](<8 x s16>)
177+
; CHECK-NEXT: $q1 = COPY [[ADD1]](<8 x s16>)
178+
%1:_(<8 x s16>) = COPY $q0
179+
%2:_(<8 x s16>) = COPY $q1
180+
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
181+
%3:_(<16 x s16>) = G_ADD %0, %0
182+
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
183+
$q0 = COPY %4(<8 x s16>)
184+
$q1 = COPY %5(<8 x s16>)
185+
186+
...
187+
---
188+
name: test_vector_add_v32s8
189+
body: |
190+
bb.0.entry:
191+
; CHECK-LABEL: name: test_vector_add_v32s8
192+
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
193+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
194+
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY]], [[COPY]]
195+
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[COPY1]], [[COPY1]]
196+
; CHECK-NEXT: $q0 = COPY [[ADD]](<16 x s8>)
197+
; CHECK-NEXT: $q1 = COPY [[ADD1]](<16 x s8>)
198+
%0:_(<16 x s8>) = COPY $q0
199+
%1:_(<16 x s8>) = COPY $q1
200+
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
201+
%3:_(<32 x s8>) = G_ADD %2, %2
202+
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
203+
$q0 = COPY %7(<16 x s8>)
204+
$q1 = COPY %8(<16 x s8>)
205+
166206
...
167207
---
168208
name: test_vector_add_nonpow2

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,46 @@ body: |
159159
G_STORE %and(s318), %ptr(p0) :: (store (s318))
160160
RET_ReallyLR implicit $x0
161161
162+
...
163+
---
164+
name: test_vector_and_v16s16
165+
body: |
166+
bb.0.entry:
167+
; CHECK-LABEL: name: test_vector_and_v16s16
168+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
169+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
170+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY]], [[COPY]]
171+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY1]], [[COPY1]]
172+
; CHECK-NEXT: $q0 = COPY [[AND]](<8 x s16>)
173+
; CHECK-NEXT: $q1 = COPY [[AND1]](<8 x s16>)
174+
%1:_(<8 x s16>) = COPY $q0
175+
%2:_(<8 x s16>) = COPY $q1
176+
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
177+
%3:_(<16 x s16>) = G_AND %0, %0
178+
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
179+
$q0 = COPY %4(<8 x s16>)
180+
$q1 = COPY %5(<8 x s16>)
181+
182+
...
183+
---
184+
name: test_vector_and_v32s8
185+
body: |
186+
bb.0.entry:
187+
; CHECK-LABEL: name: test_vector_and_v32s8
188+
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
189+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
190+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[COPY]]
191+
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY1]], [[COPY1]]
192+
; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
193+
; CHECK-NEXT: $q1 = COPY [[AND1]](<16 x s8>)
194+
%0:_(<16 x s8>) = COPY $q0
195+
%1:_(<16 x s8>) = COPY $q1
196+
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
197+
%3:_(<32 x s8>) = G_AND %2, %2
198+
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
199+
$q0 = COPY %7(<16 x s8>)
200+
$q1 = COPY %8(<16 x s8>)
201+
162202
...
163203
---
164204
name: and_v2s1

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -456,6 +456,46 @@ body: |
456456
$q0 = COPY %mul(<4 x s32>)
457457
RET_ReallyLR implicit $q0
458458
459+
...
460+
---
461+
name: test_vector_mul_v16s16
462+
body: |
463+
bb.0.entry:
464+
; CHECK-LABEL: name: test_vector_mul_v16s16
465+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
466+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
467+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY]], [[COPY]]
468+
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<8 x s16>) = G_MUL [[COPY1]], [[COPY1]]
469+
; CHECK-NEXT: $q0 = COPY [[MUL]](<8 x s16>)
470+
; CHECK-NEXT: $q1 = COPY [[MUL1]](<8 x s16>)
471+
%1:_(<8 x s16>) = COPY $q0
472+
%2:_(<8 x s16>) = COPY $q1
473+
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
474+
%3:_(<16 x s16>) = G_MUL %0, %0
475+
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
476+
$q0 = COPY %4(<8 x s16>)
477+
$q1 = COPY %5(<8 x s16>)
478+
479+
...
480+
---
481+
name: test_vector_mul_v32s8
482+
body: |
483+
bb.0.entry:
484+
; CHECK-LABEL: name: test_vector_mul_v32s8
485+
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
486+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
487+
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY]], [[COPY]]
488+
; CHECK-NEXT: [[MUL1:%[0-9]+]]:_(<16 x s8>) = G_MUL [[COPY1]], [[COPY1]]
489+
; CHECK-NEXT: $q0 = COPY [[MUL]](<16 x s8>)
490+
; CHECK-NEXT: $q1 = COPY [[MUL1]](<16 x s8>)
491+
%0:_(<16 x s8>) = COPY $q0
492+
%1:_(<16 x s8>) = COPY $q1
493+
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
494+
%3:_(<32 x s8>) = G_MUL %2, %2
495+
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
496+
$q0 = COPY %7(<16 x s8>)
497+
$q1 = COPY %8(<16 x s8>)
498+
459499
...
460500
---
461501
name: mul_v2s1

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,46 @@ body: |
9999
G_STORE %or(s318), %ptr(p0) :: (store (s318))
100100
RET_ReallyLR implicit $x0
101101
102+
...
103+
---
104+
name: test_vector_or_v16s16
105+
body: |
106+
bb.0.entry:
107+
; CHECK-LABEL: name: test_vector_or_v16s16
108+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
109+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
110+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY]], [[COPY]]
111+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY1]], [[COPY1]]
112+
; CHECK-NEXT: $q0 = COPY [[OR]](<8 x s16>)
113+
; CHECK-NEXT: $q1 = COPY [[OR1]](<8 x s16>)
114+
%1:_(<8 x s16>) = COPY $q0
115+
%2:_(<8 x s16>) = COPY $q1
116+
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
117+
%3:_(<16 x s16>) = G_OR %0, %0
118+
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
119+
$q0 = COPY %4(<8 x s16>)
120+
$q1 = COPY %5(<8 x s16>)
121+
122+
...
123+
---
124+
name: test_vector_or_v32s8
125+
body: |
126+
bb.0.entry:
127+
; CHECK-LABEL: name: test_vector_or_v32s8
128+
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
129+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
130+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY]], [[COPY]]
131+
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY1]], [[COPY1]]
132+
; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>)
133+
; CHECK-NEXT: $q1 = COPY [[OR1]](<16 x s8>)
134+
%0:_(<16 x s8>) = COPY $q0
135+
%1:_(<16 x s8>) = COPY $q1
136+
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
137+
%3:_(<32 x s8>) = G_OR %2, %2
138+
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
139+
$q0 = COPY %7(<16 x s8>)
140+
$q1 = COPY %8(<16 x s8>)
141+
102142
...
103143
---
104144
name: or_v2s1

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,46 @@ body: |
7979
%5:_(s64) = G_ANYEXT %4(s8)
8080
$x0 = COPY %5(s64)
8181
82+
...
83+
---
84+
name: test_vector_sub_v16s16
85+
body: |
86+
bb.0.entry:
87+
; CHECK-LABEL: name: test_vector_sub_v16s16
88+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
89+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
90+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY]], [[COPY]]
91+
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<8 x s16>) = G_SUB [[COPY1]], [[COPY1]]
92+
; CHECK-NEXT: $q0 = COPY [[SUB]](<8 x s16>)
93+
; CHECK-NEXT: $q1 = COPY [[SUB1]](<8 x s16>)
94+
%1:_(<8 x s16>) = COPY $q0
95+
%2:_(<8 x s16>) = COPY $q1
96+
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
97+
%3:_(<16 x s16>) = G_SUB %0, %0
98+
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
99+
$q0 = COPY %4(<8 x s16>)
100+
$q1 = COPY %5(<8 x s16>)
101+
102+
...
103+
---
104+
name: test_vector_sub_v32s8
105+
body: |
106+
bb.0.entry:
107+
; CHECK-LABEL: name: test_vector_sub_v32s8
108+
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
109+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
110+
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY]], [[COPY]]
111+
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY1]], [[COPY1]]
112+
; CHECK-NEXT: $q0 = COPY [[SUB]](<16 x s8>)
113+
; CHECK-NEXT: $q1 = COPY [[SUB1]](<16 x s8>)
114+
%0:_(<16 x s8>) = COPY $q0
115+
%1:_(<16 x s8>) = COPY $q1
116+
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
117+
%3:_(<32 x s8>) = G_SUB %2, %2
118+
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
119+
$q0 = COPY %7(<16 x s8>)
120+
$q1 = COPY %8(<16 x s8>)
121+
82122
...
83123
---
84124
name: sub_v2s1

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,46 @@ body: |
146146
G_STORE %xor(s158), %ptr(p0) :: (store (s158))
147147
RET_ReallyLR implicit $x0
148148
149+
...
150+
---
151+
name: test_vector_xor_v16s16
152+
body: |
153+
bb.0.entry:
154+
; CHECK-LABEL: name: test_vector_xor_v16s16
155+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
156+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
157+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[COPY]], [[COPY]]
158+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<8 x s16>) = G_XOR [[COPY1]], [[COPY1]]
159+
; CHECK-NEXT: $q0 = COPY [[XOR]](<8 x s16>)
160+
; CHECK-NEXT: $q1 = COPY [[XOR1]](<8 x s16>)
161+
%1:_(<8 x s16>) = COPY $q0
162+
%2:_(<8 x s16>) = COPY $q1
163+
%0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
164+
%3:_(<16 x s16>) = G_XOR %0, %0
165+
%4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
166+
$q0 = COPY %4(<8 x s16>)
167+
$q1 = COPY %5(<8 x s16>)
168+
169+
...
170+
---
171+
name: test_vector_xor_v32s8
172+
body: |
173+
bb.0.entry:
174+
; CHECK-LABEL: name: test_vector_xor_v32s8
175+
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
176+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
177+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[COPY]], [[COPY]]
178+
; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s8>) = G_XOR [[COPY1]], [[COPY1]]
179+
; CHECK-NEXT: $q0 = COPY [[XOR]](<16 x s8>)
180+
; CHECK-NEXT: $q1 = COPY [[XOR1]](<16 x s8>)
181+
%0:_(<16 x s8>) = COPY $q0
182+
%1:_(<16 x s8>) = COPY $q1
183+
%2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
184+
%3:_(<32 x s8>) = G_XOR %2, %2
185+
%7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
186+
$q0 = COPY %7(<16 x s8>)
187+
$q1 = COPY %8(<16 x s8>)
188+
149189
...
150190
---
151191
name: xor_v2s1

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