@@ -5159,6 +5159,42 @@ LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
5159
5159
return Legalized;
5160
5160
}
5161
5161
5162
+ MachineInstrBuilder LegalizerHelper::getNeutralElementForVecReduce (
5163
+ unsigned Opcode, MachineIRBuilder &MIRBuilder, LLT Ty) {
5164
+ assert (Ty.isScalar () && " Expected scalar type to make neutral element for" );
5165
+
5166
+ switch (Opcode) {
5167
+ default :
5168
+ return MIRBuilder.buildUndef (Ty);
5169
+ case TargetOpcode::G_VECREDUCE_ADD:
5170
+ case TargetOpcode::G_VECREDUCE_OR:
5171
+ case TargetOpcode::G_VECREDUCE_XOR:
5172
+ case TargetOpcode::G_VECREDUCE_UMAX:
5173
+ return MIRBuilder.buildConstant (Ty, 0 );
5174
+ case TargetOpcode::G_VECREDUCE_MUL:
5175
+ return MIRBuilder.buildConstant (Ty, 1 );
5176
+ case TargetOpcode::G_VECREDUCE_AND:
5177
+ case TargetOpcode::G_VECREDUCE_UMIN:
5178
+ return MIRBuilder.buildConstant (
5179
+ Ty, APInt::getAllOnes (Ty.getScalarSizeInBits ()));
5180
+ case TargetOpcode::G_VECREDUCE_SMAX:
5181
+ return MIRBuilder.buildConstant (
5182
+ Ty, APInt::getSignedMinValue (Ty.getSizeInBits ()));
5183
+ case TargetOpcode::G_VECREDUCE_SMIN:
5184
+ return MIRBuilder.buildConstant (
5185
+ Ty, APInt::getSignedMaxValue (Ty.getSizeInBits ()));
5186
+ case TargetOpcode::G_VECREDUCE_FADD:
5187
+ return MIRBuilder.buildFConstant (Ty, -0.0 );
5188
+ case TargetOpcode::G_VECREDUCE_FMUL:
5189
+ return MIRBuilder.buildFConstant (Ty, 1.0 );
5190
+ case TargetOpcode::G_VECREDUCE_FMINIMUM:
5191
+ case TargetOpcode::G_VECREDUCE_FMAXIMUM:
5192
+ assert (false && " getNeutralElementForVecReduce unimplemented for "
5193
+ " G_VECREDUCE_FMINIMUM and G_VECREDUCE_FMAXIMUM!" );
5194
+ }
5195
+ llvm_unreachable (" switch expected to return!" );
5196
+ }
5197
+
5162
5198
LegalizerHelper::LegalizeResult
5163
5199
LegalizerHelper::moreElementsVector (MachineInstr &MI, unsigned TypeIdx,
5164
5200
LLT MoreTy) {
@@ -5341,6 +5377,35 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
5341
5377
Observer.changedInstr (MI);
5342
5378
return Legalized;
5343
5379
}
5380
+ case TargetOpcode::G_VECREDUCE_FADD:
5381
+ case TargetOpcode::G_VECREDUCE_FMUL:
5382
+ case TargetOpcode::G_VECREDUCE_ADD:
5383
+ case TargetOpcode::G_VECREDUCE_MUL:
5384
+ case TargetOpcode::G_VECREDUCE_AND:
5385
+ case TargetOpcode::G_VECREDUCE_OR:
5386
+ case TargetOpcode::G_VECREDUCE_XOR:
5387
+ case TargetOpcode::G_VECREDUCE_SMAX:
5388
+ case TargetOpcode::G_VECREDUCE_SMIN:
5389
+ case TargetOpcode::G_VECREDUCE_UMAX:
5390
+ case TargetOpcode::G_VECREDUCE_UMIN: {
5391
+ LLT OrigTy = MRI.getType (MI.getOperand (1 ).getReg ());
5392
+ MachineOperand &MO = MI.getOperand (1 );
5393
+ auto NewVec = MIRBuilder.buildPadVectorWithUndefElements (MoreTy, MO);
5394
+ auto NeutralElement = getNeutralElementForVecReduce (
5395
+ MI.getOpcode (), MIRBuilder, MoreTy.getElementType ());
5396
+ for (size_t i = OrigTy.getNumElements (), e = MoreTy.getNumElements ();
5397
+ i != e; i++) {
5398
+ auto Idx = MIRBuilder.buildConstant (LLT::scalar (32 ), i);
5399
+ NewVec = MIRBuilder.buildInsertVectorElement (MoreTy, NewVec,
5400
+ NeutralElement, Idx);
5401
+ }
5402
+
5403
+ Observer.changingInstr (MI);
5404
+ MO.setReg (NewVec.getReg (0 ));
5405
+ Observer.changedInstr (MI);
5406
+ return Legalized;
5407
+ }
5408
+
5344
5409
default :
5345
5410
return UnableToLegalize;
5346
5411
}
0 commit comments