[SelectionDAG] soften assertion when legalizing narrow vector FP ops

The test based on PR42010:
https://bugs.llvm.org/show_bug.cgi?id=42010
...may show an inaccuracy for PPC's target defs, but we should not
be so aggressive with an assert here. There's no telling what out-of-tree
targets look like.

llvm-svn: 361696

Author: rotateright

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -2743,13 +2743,11 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
     // We're going to widen this vector op to a legal type by padding with undef
     // elements. If the wide vector op is eventually going to be expanded to
     // scalar libcalls, then unroll into scalar ops now to avoid unnecessary
-    // libcalls on the undef elements. We are assuming that if the scalar op
-    // requires expanding, then the vector op needs expanding too.
+    // libcalls on the undef elements.
     EVT VT = N->getValueType(0);
-    if (TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
-      EVT WideVecVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
-      assert(!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) &&
-             "Target supports vector op, but scalar requires expansion?");
+    EVT WideVecVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+    if (!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) &&
+        TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
       Res = DAG.UnrollVectorOp(N, WideVecVT.getVectorNumElements());
       break;
     }

llvm/test/CodeGen/PowerPC/ftrunc-legalize.ll

@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64-- -mattr=altivec -verify-machineinstrs < %s | FileCheck %s
+
+; This would assert because the widened vector op is
+; legal/custom, but the scalar op is expanded.
+
+define i32 @PR42010(<2 x float> %x) {
+; CHECK-LABEL: PR42010:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi 3, 1, -32
+; CHECK-NEXT:    vrfiz 2, 2
+; CHECK-NEXT:    stvx 2, 0, 3
+; CHECK-NEXT:    lfs 0, -28(1)
+; CHECK-NEXT:    fctiwz 0, 0
+; CHECK-NEXT:    stfd 0, -8(1)
+; CHECK-NEXT:    lwz 3, -4(1)
+; CHECK-NEXT:    blr
+  %t0 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %x)
+  %t1 = extractelement <2 x float> %t0, i32 1
+  %t2 = fptosi float %t1 to i32
+  ret i32 %t2
+}
+
+declare <2 x float> @llvm.trunc.v2f32(<2 x float>)