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davemgreendavemgreen
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Attempt to use LocationSize
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71 files changed

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‎llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -647,15 +647,15 @@ bool GIMatchTableExecutor::executeMatchTable(
647647

648648
unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
649649
if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
650-
MMO->getSizeInBits() != Size) {
650+
MMO->getSizeInBits().getValue() != Size) {
651651
if (handleReject() == RejectAndGiveUp)
652652
return false;
653653
} else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
654-
MMO->getSizeInBits() >= Size) {
654+
MMO->getSizeInBits().getValue() >= Size) {
655655
if (handleReject() == RejectAndGiveUp)
656656
return false;
657657
} else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
658-
MMO->getSizeInBits() <= Size)
658+
MMO->getSizeInBits().getValue() <= Size)
659659
if (handleReject() == RejectAndGiveUp)
660660
return false;
661661

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,9 +54,9 @@ class GMemOperation : public GenericMachineInstr {
5454
bool isUnordered() const { return getMMO().isUnordered(); }
5555

5656
/// Returns the size in bytes of the memory access.
57-
uint64_t getMemSize() const { return getMMO().getSize(); }
57+
LocationSize getMemSize() const { return getMMO().getSize(); }
5858
/// Returns the size in bits of the memory access.
59-
uint64_t getMemSizeInBits() const { return getMMO().getSizeInBits(); }
59+
LocationSize getMemSizeInBits() const { return getMMO().getSizeInBits(); }
6060

6161
static bool classof(const MachineInstr *MI) {
6262
return GenericMachineInstr::classof(MI) && MI->hasOneMemOperand();

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 41 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1026,25 +1026,37 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10261026
/// MachineMemOperands are owned by the MachineFunction and need not be
10271027
/// explicitly deallocated.
10281028
MachineMemOperand *getMachineMemOperand(
1029-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s,
1029+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy,
10301030
Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
10311031
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10321032
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
10331033
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
1034-
10351034
MachineMemOperand *getMachineMemOperand(
1036-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
1035+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, LocationSize TS,
10371036
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
10381037
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10391038
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
10401039
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
1041-
10421040
MachineMemOperand *getMachineMemOperand(
1043-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy,
1044-
Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
1041+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, uint64_t TS,
1042+
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
10451043
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10461044
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
1047-
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
1045+
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic) {
1046+
return getMachineMemOperand(PtrInfo, F, LocationSize::precise(TS),
1047+
BaseAlignment, AAInfo, Ranges, SSID, Ordering,
1048+
FailureOrdering);
1049+
}
1050+
MachineMemOperand *getMachineMemOperand(
1051+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
1052+
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
1053+
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
1054+
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
1055+
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic) {
1056+
return getMachineMemOperand(PtrInfo, F, LocationSize::precise(TS),
1057+
BaseAlignment, AAInfo, Ranges, SSID, Ordering,
1058+
FailureOrdering);
1059+
}
10481060

10491061
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
10501062
/// an existing one, adjusting by an offset and using the given size.
@@ -1053,18 +1065,21 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10531065
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10541066
int64_t Offset, LLT Ty);
10551067
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1056-
int64_t Offset, uint64_t Size) {
1068+
int64_t Offset, LocationSize TS) {
10571069
return getMachineMemOperand(
1058-
MMO, Offset, Size == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * Size));
1070+
MMO, Offset,
1071+
!TS.hasValue() ? LLT()
1072+
: TS.isScalable()
1073+
? LLT::scalable_vector(1, 8 * TS.getValue().getKnownMinValue())
1074+
: LLT::scalar(8 * TS.getValue().getKnownMinValue()));
10591075
}
1060-
10611076
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1062-
int64_t Offset, TypeSize TS) {
1063-
return getMachineMemOperand(
1064-
MMO, Offset,
1065-
TS.getKnownMinValue() == ~UINT64_C(0) ? LLT()
1066-
: TS.isScalable() ? LLT::scalable_vector(1, 8 * TS.getKnownMinValue())
1067-
: LLT::scalar(8 * TS.getKnownMinValue()));
1077+
int64_t Offset, uint64_t Size) {
1078+
return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
1079+
}
1080+
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1081+
int64_t Offset, TypeSize Size) {
1082+
return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
10681083
}
10691084

10701085
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
@@ -1073,13 +1088,20 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10731088
/// explicitly deallocated.
10741089
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10751090
const MachinePointerInfo &PtrInfo,
1076-
uint64_t Size);
1091+
LocationSize TS);
10771092
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10781093
const MachinePointerInfo &PtrInfo,
1079-
TypeSize TS);
1094+
LLT Ty);
10801095
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10811096
const MachinePointerInfo &PtrInfo,
1082-
LLT Ty);
1097+
uint64_t Size) {
1098+
return getMachineMemOperand(MMO, PtrInfo, LocationSize::precise(Size));
1099+
}
1100+
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1101+
const MachinePointerInfo &PtrInfo,
1102+
TypeSize Size) {
1103+
return getMachineMemOperand(MMO, PtrInfo, LocationSize::precise(Size));
1104+
}
10831105

10841106
/// Allocate a new MachineMemOperand by copying an existing one,
10851107
/// replacing only AliasAnalysis information. MachineMemOperands are owned

‎llvm/include/llvm/CodeGen/MachineInstr.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1744,16 +1744,17 @@ class MachineInstr
17441744
bool allImplicitDefsAreDead() const;
17451745

17461746
/// Return a valid size if the instruction is a spill instruction.
1747-
std::optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1747+
std::optional<LocationSize> getSpillSize(const TargetInstrInfo *TII) const;
17481748

17491749
/// Return a valid size if the instruction is a folded spill instruction.
1750-
std::optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1750+
std::optional<LocationSize>
1751+
getFoldedSpillSize(const TargetInstrInfo *TII) const;
17511752

17521753
/// Return a valid size if the instruction is a restore instruction.
1753-
std::optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1754+
std::optional<LocationSize> getRestoreSize(const TargetInstrInfo *TII) const;
17541755

17551756
/// Return a valid size if the instruction is a folded restore instruction.
1756-
std::optional<unsigned>
1757+
std::optional<LocationSize>
17571758
getFoldedRestoreSize(const TargetInstrInfo *TII) const;
17581759

17591760
/// Copy implicit register operands from specified

‎llvm/include/llvm/CodeGen/MachineMemOperand.h

Lines changed: 10 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717

1818
#include "llvm/ADT/BitmaskEnum.h"
1919
#include "llvm/ADT/PointerUnion.h"
20+
#include "llvm/Analysis/MemoryLocation.h"
2021
#include "llvm/CodeGen/LowLevelType.h"
2122
#include "llvm/CodeGen/PseudoSourceValue.h"
2223
#include "llvm/IR/DerivedTypes.h"
@@ -186,13 +187,7 @@ class MachineMemOperand {
186187
/// and atomic ordering requirements must also be specified. For cmpxchg
187188
/// atomic operations the atomic ordering requirements when store does not
188189
/// occur must also be specified.
189-
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
190-
Align a, const AAMDNodes &AAInfo = AAMDNodes(),
191-
const MDNode *Ranges = nullptr,
192-
SyncScope::ID SSID = SyncScope::System,
193-
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
194-
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
195-
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, TypeSize TS,
190+
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LocationSize TS,
196191
Align a, const AAMDNodes &AAInfo = AAMDNodes(),
197192
const MDNode *Ranges = nullptr,
198193
SyncScope::ID SSID = SyncScope::System,
@@ -241,15 +236,17 @@ class MachineMemOperand {
241236
LLT getMemoryType() const { return MemoryType; }
242237

243238
/// Return the size in bytes of the memory reference.
244-
TypeSize getSize() const {
245-
return MemoryType.isValid() ? MemoryType.getSizeInBytes()
246-
: TypeSize::Fixed(~UINT64_C(0));
239+
LocationSize getSize() const {
240+
return MemoryType.isValid()
241+
? LocationSize::precise(MemoryType.getSizeInBytes())
242+
: LocationSize::beforeOrAfterPointer();
247243
}
248244

249245
/// Return the size in bits of the memory reference.
250-
TypeSize getSizeInBits() const {
251-
return MemoryType.isValid() ? MemoryType.getSizeInBits()
252-
: TypeSize::Fixed(~UINT64_C(0));
246+
LocationSize getSizeInBits() const {
247+
return MemoryType.isValid()
248+
? LocationSize::precise(MemoryType.getSizeInBits())
249+
: LocationSize::beforeOrAfterPointer();
253250
}
254251

255252
LLT getType() const {

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1297,15 +1297,15 @@ class SelectionDAG {
12971297
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
12981298
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
12991299
MachineMemOperand::MOStore,
1300-
uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes());
1300+
LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes());
13011301

13021302
inline SDValue getMemIntrinsicNode(
13031303
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
13041304
EVT MemVT, MachinePointerInfo PtrInfo,
13051305
MaybeAlign Alignment = std::nullopt,
13061306
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
13071307
MachineMemOperand::MOStore,
1308-
uint64_t Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
1308+
LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
13091309
// Ensure that codegen never sees alignment 0
13101310
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
13111311
Alignment.value_or(getEVTAlign(MemVT)), Flags,

‎llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -81,10 +81,8 @@ class BaseIndexOffset {
8181

8282
// Returns true `Op0` and `Op1` can be proven to alias/not alias, in
8383
// which case `IsAlias` is set to true/false.
84-
static bool computeAliasing(const SDNode *Op0,
85-
const std::optional<TypeSize> NumBytes0,
86-
const SDNode *Op1,
87-
const std::optional<TypeSize> NumBytes1,
84+
static bool computeAliasing(const SDNode *Op0, const LocationSize NumBytes0,
85+
const SDNode *Op1, const LocationSize NumBytes1,
8886
const SelectionDAG &DAG, bool &IsAlias);
8987

9088
/// Parses tree in N for base, index, offset addresses.

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1433,7 +1433,7 @@ class TargetInstrInfo : public MCInstrInfo {
14331433
/// abstraction that supports negative offsets.
14341434
virtual bool getMemOperandsWithOffsetWidth(
14351435
const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
1436-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
1436+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
14371437
const TargetRegisterInfo *TRI) const {
14381438
return false;
14391439
}

‎llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Lines changed: 11 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1098,25 +1098,21 @@ static void emitComments(const MachineInstr &MI, raw_ostream &CommentOS) {
10981098

10991099
// We assume a single instruction only has a spill or reload, not
11001100
// both.
1101-
std::optional<unsigned> Size;
1101+
std::optional<LocationSize> Size;
11021102
if ((Size = MI.getRestoreSize(TII))) {
1103-
CommentOS << *Size << "-byte Reload\n";
1103+
CommentOS << Size->getValue() << "-byte Reload\n";
11041104
} else if ((Size = MI.getFoldedRestoreSize(TII))) {
1105-
if (*Size) {
1106-
if (*Size == unsigned(MemoryLocation::UnknownSize))
1107-
CommentOS << "Unknown-size Folded Reload\n";
1108-
else
1109-
CommentOS << *Size << "-byte Folded Reload\n";
1110-
}
1105+
if (!Size->hasValue())
1106+
CommentOS << "Unknown-size Folded Reload\n";
1107+
else if (Size->getValue())
1108+
CommentOS << Size->getValue() << "-byte Folded Reload\n";
11111109
} else if ((Size = MI.getSpillSize(TII))) {
1112-
CommentOS << *Size << "-byte Spill\n";
1110+
CommentOS << Size->getValue() << "-byte Spill\n";
11131111
} else if ((Size = MI.getFoldedSpillSize(TII))) {
1114-
if (*Size) {
1115-
if (*Size == unsigned(MemoryLocation::UnknownSize))
1116-
CommentOS << "Unknown-size Folded Spill\n";
1117-
else
1118-
CommentOS << *Size << "-byte Folded Spill\n";
1119-
}
1112+
if (!Size->hasValue())
1113+
CommentOS << "Unknown-size Folded Spill\n";
1114+
else if (Size->getValue())
1115+
CommentOS << Size->getValue() << "-byte Folded Spill\n";
11201116
}
11211117

11221118
// Check for spill-induced copies

‎llvm/lib/CodeGen/DFAPacketizer.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -252,12 +252,13 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
252252
bool VLIWPacketizerList::alias(const MachineMemOperand &Op1,
253253
const MachineMemOperand &Op2,
254254
bool UseTBAA) const {
255-
if (!Op1.getValue() || !Op2.getValue())
255+
if (!Op1.getValue() || !Op2.getValue() || !Op1.getSize().hasValue() ||
256+
!Op2.getSize().hasValue())
256257
return true;
257258

258259
int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset());
259-
int64_t Overlapa = Op1.getSize() + Op1.getOffset() - MinOffset;
260-
int64_t Overlapb = Op2.getSize() + Op2.getOffset() - MinOffset;
260+
int64_t Overlapa = Op1.getSize().getValue() + Op1.getOffset() - MinOffset;
261+
int64_t Overlapb = Op2.getSize().getValue() + Op2.getOffset() - MinOffset;
261262

262263
AliasResult AAResult =
263264
AA->alias(MemoryLocation(Op1.getValue(), Overlapa,

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -764,12 +764,12 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
764764
LLT RegTy = MRI.getType(LoadReg);
765765
Register PtrReg = LoadMI->getPointerReg();
766766
unsigned RegSize = RegTy.getSizeInBits();
767-
uint64_t LoadSizeBits = LoadMI->getMemSizeInBits();
767+
LocationSize LoadSizeBits = LoadMI->getMemSizeInBits();
768768
unsigned MaskSizeBits = MaskVal.countr_one();
769769

770770
// The mask may not be larger than the in-memory type, as it might cover sign
771771
// extended bits
772-
if (MaskSizeBits > LoadSizeBits)
772+
if (MaskSizeBits > LoadSizeBits.getValue())
773773
return false;
774774

775775
// If the mask covers the whole destination register, there's nothing to
@@ -789,7 +789,8 @@ bool CombinerHelper::matchCombineLoadWithAndMask(MachineInstr &MI,
789789
// still adjust the opcode to indicate the high bit behavior.
790790
if (LoadMI->isSimple())
791791
MemDesc.MemoryTy = LLT::scalar(MaskSizeBits);
792-
else if (LoadSizeBits > MaskSizeBits || LoadSizeBits == RegSize)
792+
else if (LoadSizeBits.getValue() > MaskSizeBits ||
793+
LoadSizeBits.getValue() == RegSize)
793794
return false;
794795

795796
// TODO: Could check if it's legal with the reduced or original memory size.
@@ -854,7 +855,8 @@ bool CombinerHelper::matchSextTruncSextLoad(MachineInstr &MI) {
854855
if (auto *LoadMI = getOpcodeDef<GSExtLoad>(LoadUser, MRI)) {
855856
// If truncating more than the original extended value, abort.
856857
auto LoadSizeBits = LoadMI->getMemSizeInBits();
857-
if (TruncSrc && MRI.getType(TruncSrc).getSizeInBits() < LoadSizeBits)
858+
if (TruncSrc &&
859+
MRI.getType(TruncSrc).getSizeInBits() < LoadSizeBits.getValue())
858860
return false;
859861
if (LoadSizeBits == SizeInBits)
860862
return true;
@@ -885,7 +887,7 @@ bool CombinerHelper::matchSextInRegOfLoad(
885887
if (!LoadDef || !MRI.hasOneNonDBGUse(DstReg))
886888
return false;
887889

888-
uint64_t MemBits = LoadDef->getMemSizeInBits();
890+
uint64_t MemBits = LoadDef->getMemSizeInBits().getValue();
889891

890892
// If the sign extend extends from a narrower width than the load's width,
891893
// then we can narrow the load width when we combine to a G_SEXTLOAD.

‎llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -415,7 +415,8 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
415415
if (DstTy.isVector())
416416
break;
417417
// Everything above the retrieved bits is zero
418-
Known.Zero.setBitsFrom((*MI.memoperands_begin())->getSizeInBits());
418+
Known.Zero.setBitsFrom(
419+
(*MI.memoperands_begin())->getSizeInBits().getValue());
419420
break;
420421
}
421422
case TargetOpcode::G_ASHR: {
@@ -666,7 +667,7 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
666667

667668
// e.g. i16->i32 = '17' bits known.
668669
const MachineMemOperand *MMO = *MI.memoperands_begin();
669-
return TyBits - MMO->getSizeInBits() + 1;
670+
return TyBits - MMO->getSizeInBits().getValue() + 1;
670671
}
671672
case TargetOpcode::G_ZEXTLOAD: {
672673
// FIXME: We need an in-memory type representation.
@@ -675,7 +676,7 @@ unsigned GISelKnownBits::computeNumSignBits(Register R,
675676

676677
// e.g. i16->i32 = '16' bits known.
677678
const MachineMemOperand *MMO = *MI.memoperands_begin();
678-
return TyBits - MMO->getSizeInBits();
679+
return TyBits - MMO->getSizeInBits().getValue();
679680
}
680681
case TargetOpcode::G_TRUNC: {
681682
Register Src = MI.getOperand(1).getReg();

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