@@ -115,29 +115,30 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
115
115
Val >>= ShiftAmount;
116
116
117
117
// If the remaining bits don't fit in 12 bits, we might be able to reduce
118
- // the shift amount in order to use LUI which will zero the lower 12 bits.
118
+ // the // shift amount in order to use LUI which will zero the lower 12
119
+ // bits.
119
120
if (ShiftAmount > 12 && !isInt<12 >(Val)) {
120
- if (isInt<32 >(Val << 12 )) {
121
+ if (isInt<32 >(( uint64_t ) Val << 12 )) {
121
122
// Reduce the shift amount and add zeros to the LSBs so it will match
122
123
// LUI.
123
124
ShiftAmount -= 12 ;
124
- Val = Val << 12 ;
125
- } else if (isUInt<32 >(Val << 12 ) &&
125
+ Val = ( uint64_t ) Val << 12 ;
126
+ } else if (isUInt<32 >(( uint64_t ) Val << 12 ) &&
126
127
STI.hasFeature (RISCV::FeatureStdExtZba)) {
127
128
// Reduce the shift amount and add zeros to the LSBs so it will match
128
129
// LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
129
130
ShiftAmount -= 12 ;
130
- Val = SignExtend64< 32 >( Val << 12 );
131
+ Val = (( uint64_t ) Val << 12 ) | ( 0xffffffffull << 32 );
131
132
Unsigned = true ;
132
133
}
133
134
}
134
135
135
136
// Try to use SLLI_UW for Val when it is uint32 but not int32.
136
- if (isUInt<32 >(Val) && !isInt<32 >(Val) &&
137
+ if (isUInt<32 >(( uint64_t ) Val) && !isInt<32 >(( uint64_t ) Val) &&
137
138
STI.hasFeature (RISCV::FeatureStdExtZba)) {
138
- // Use LUI+ADDI(W) or LUI to compose, then clear the upper 32 bits with
139
+ // Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
139
140
// SLLI_UW.
140
- Val = SignExtend64< 32 >( Val);
141
+ Val = (( uint64_t ) Val) | ( 0xffffffffull << 32 );
141
142
Unsigned = true ;
142
143
}
143
144
}
0 commit comments