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[RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32
In our default SelectionDAG where i32 isn't legal, the zext will become and i64 AND and often get optimized out on its own. With i32 legal, we need to turn it in into sext.w and rely on RISCVOptWInstrs to remove it.
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-37
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5 files changed

+9
-37
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2014,6 +2014,11 @@ def as_i64imm : SDNodeXForm<imm, [{
20142014
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
20152015
}]>;
20162016

2017+
def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
2018+
KnownBits Known = CurDAG->computeKnownBits(N->getOperand(0), 0);
2019+
return Known.isNonNegative();
2020+
}]>;
2021+
20172022
let Predicates = [IsRV64] in {
20182023
def : LdPat<sextloadi8, LB, i32>;
20192024
def : LdPat<extloadi8, LBU, i32>; // Prefer unsigned due to no c.lb in Zcb.
@@ -2054,6 +2059,9 @@ def : PatGprImm<sra, SRAIW, uimm5, i32>;
20542059
def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
20552060
(SRLI (SLLI $rs, (i64 (XLenSubTrailingOnes $mask))),
20562061
(i64 (XLenSubTrailingOnes $mask)))>;
2062+
2063+
// Use sext if the sign bit of the input is 0.
2064+
def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
20572065
}
20582066

20592067
let Predicates = [IsRV64, NotHasStdExtZba] in {

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll

Lines changed: 0 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -302,8 +302,6 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
302302
; RV64XTHEADBB-LABEL: ctlz_lshr_i32:
303303
; RV64XTHEADBB: # %bb.0:
304304
; RV64XTHEADBB-NEXT: srliw a0, a0, 1
305-
; RV64XTHEADBB-NEXT: slli a0, a0, 32
306-
; RV64XTHEADBB-NEXT: srli a0, a0, 32
307305
; RV64XTHEADBB-NEXT: th.ff1 a0, a0
308306
; RV64XTHEADBB-NEXT: addi a0, a0, -32
309307
; RV64XTHEADBB-NEXT: ret
@@ -392,8 +390,6 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
392390
; RV64I-NEXT: addiw a1, a1, 1329
393391
; RV64I-NEXT: call __muldi3@plt
394392
; RV64I-NEXT: srliw a0, a0, 27
395-
; RV64I-NEXT: slli a0, a0, 32
396-
; RV64I-NEXT: srli a0, a0, 32
397393
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
398394
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
399395
; RV64I-NEXT: add a0, a1, a0
@@ -417,8 +413,6 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
417413
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
418414
; RV64XTHEADBB-NEXT: call __muldi3@plt
419415
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
420-
; RV64XTHEADBB-NEXT: slli a0, a0, 32
421-
; RV64XTHEADBB-NEXT: srli a0, a0, 32
422416
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI6_0)
423417
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI6_0)
424418
; RV64XTHEADBB-NEXT: add a0, a1, a0
@@ -448,8 +442,6 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
448442
; RV64I-NEXT: addiw a1, a1, 1329
449443
; RV64I-NEXT: call __muldi3@plt
450444
; RV64I-NEXT: srliw a0, a0, 27
451-
; RV64I-NEXT: slli a0, a0, 32
452-
; RV64I-NEXT: srli a0, a0, 32
453445
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
454446
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)
455447
; RV64I-NEXT: add a0, a1, a0
@@ -468,8 +460,6 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
468460
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
469461
; RV64XTHEADBB-NEXT: call __muldi3@plt
470462
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
471-
; RV64XTHEADBB-NEXT: slli a0, a0, 32
472-
; RV64XTHEADBB-NEXT: srli a0, a0, 32
473463
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI7_0)
474464
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI7_0)
475465
; RV64XTHEADBB-NEXT: add a0, a1, a0
@@ -494,8 +484,6 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
494484
; RV64I-NEXT: addiw a1, a1, 1329
495485
; RV64I-NEXT: call __muldi3@plt
496486
; RV64I-NEXT: srliw a0, a0, 27
497-
; RV64I-NEXT: slli a0, a0, 32
498-
; RV64I-NEXT: srli a0, a0, 32
499487
; RV64I-NEXT: lui a1, %hi(.LCPI8_0)
500488
; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0)
501489
; RV64I-NEXT: add a0, a1, a0
@@ -520,8 +508,6 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
520508
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
521509
; RV64XTHEADBB-NEXT: call __muldi3@plt
522510
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
523-
; RV64XTHEADBB-NEXT: slli a0, a0, 32
524-
; RV64XTHEADBB-NEXT: srli a0, a0, 32
525511
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI8_0)
526512
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI8_0)
527513
; RV64XTHEADBB-NEXT: add a0, a1, a0
@@ -552,8 +538,6 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
552538
; RV64I-NEXT: addiw a1, a1, 1329
553539
; RV64I-NEXT: call __muldi3@plt
554540
; RV64I-NEXT: srliw a0, a0, 27
555-
; RV64I-NEXT: slli a0, a0, 32
556-
; RV64I-NEXT: srli a0, a0, 32
557541
; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
558542
; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
559543
; RV64I-NEXT: add a0, a1, a0
@@ -581,8 +565,6 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
581565
; RV64XTHEADBB-NEXT: addiw a1, a1, 1329
582566
; RV64XTHEADBB-NEXT: call __muldi3@plt
583567
; RV64XTHEADBB-NEXT: srliw a0, a0, 27
584-
; RV64XTHEADBB-NEXT: slli a0, a0, 32
585-
; RV64XTHEADBB-NEXT: srli a0, a0, 32
586568
; RV64XTHEADBB-NEXT: lui a1, %hi(.LCPI9_0)
587569
; RV64XTHEADBB-NEXT: addi a1, a1, %lo(.LCPI9_0)
588570
; RV64XTHEADBB-NEXT: add a0, a1, a0

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1521,7 +1521,6 @@ define signext i32 @srliw_1_sh2add(ptr %0, i32 signext %1) {
15211521
; RV64ZBA-LABEL: srliw_1_sh2add:
15221522
; RV64ZBA: # %bb.0:
15231523
; RV64ZBA-NEXT: srliw a1, a1, 1
1524-
; RV64ZBA-NEXT: zext.w a1, a1
15251524
; RV64ZBA-NEXT: sh2add a0, a1, a0
15261525
; RV64ZBA-NEXT: lw a0, 0(a0)
15271526
; RV64ZBA-NEXT: ret
@@ -1545,7 +1544,6 @@ define i64 @srliw_1_sh3add(ptr %0, i32 signext %1) {
15451544
; RV64ZBA-LABEL: srliw_1_sh3add:
15461545
; RV64ZBA: # %bb.0:
15471546
; RV64ZBA-NEXT: srliw a1, a1, 1
1548-
; RV64ZBA-NEXT: zext.w a1, a1
15491547
; RV64ZBA-NEXT: sh3add a0, a1, a0
15501548
; RV64ZBA-NEXT: ld a0, 0(a0)
15511549
; RV64ZBA-NEXT: ret
@@ -1569,7 +1567,6 @@ define i64 @srliw_2_sh3add(ptr %0, i32 signext %1) {
15691567
; RV64ZBA-LABEL: srliw_2_sh3add:
15701568
; RV64ZBA: # %bb.0:
15711569
; RV64ZBA-NEXT: srliw a1, a1, 2
1572-
; RV64ZBA-NEXT: zext.w a1, a1
15731570
; RV64ZBA-NEXT: sh3add a0, a1, a0
15741571
; RV64ZBA-NEXT: ld a0, 0(a0)
15751572
; RV64ZBA-NEXT: ret
@@ -1593,7 +1590,6 @@ define signext i16 @srliw_2_sh1add(ptr %0, i32 signext %1) {
15931590
; RV64ZBA-LABEL: srliw_2_sh1add:
15941591
; RV64ZBA: # %bb.0:
15951592
; RV64ZBA-NEXT: srliw a1, a1, 2
1596-
; RV64ZBA-NEXT: zext.w a1, a1
15971593
; RV64ZBA-NEXT: sh1add a0, a1, a0
15981594
; RV64ZBA-NEXT: lh a0, 0(a0)
15991595
; RV64ZBA-NEXT: ret
@@ -1618,7 +1614,6 @@ define signext i32 @srliw_3_sh2add(ptr %0, i32 signext %1) {
16181614
; RV64ZBA-LABEL: srliw_3_sh2add:
16191615
; RV64ZBA: # %bb.0:
16201616
; RV64ZBA-NEXT: srliw a1, a1, 3
1621-
; RV64ZBA-NEXT: zext.w a1, a1
16221617
; RV64ZBA-NEXT: sh2add a0, a1, a0
16231618
; RV64ZBA-NEXT: lw a0, 0(a0)
16241619
; RV64ZBA-NEXT: ret
@@ -1642,7 +1637,6 @@ define i64 @srliw_4_sh3add(ptr %0, i32 signext %1) {
16421637
; RV64ZBA-LABEL: srliw_4_sh3add:
16431638
; RV64ZBA: # %bb.0:
16441639
; RV64ZBA-NEXT: srliw a1, a1, 4
1645-
; RV64ZBA-NEXT: zext.w a1, a1
16461640
; RV64ZBA-NEXT: sh3add a0, a1, a0
16471641
; RV64ZBA-NEXT: ld a0, 0(a0)
16481642
; RV64ZBA-NEXT: ret

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -380,8 +380,6 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
380380
; RV64I-NEXT: addiw a1, a1, 1329
381381
; RV64I-NEXT: call __muldi3@plt
382382
; RV64I-NEXT: srliw a0, a0, 27
383-
; RV64I-NEXT: slli a0, a0, 32
384-
; RV64I-NEXT: srli a0, a0, 32
385383
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
386384
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
387385
; RV64I-NEXT: add a0, a1, a0
@@ -412,8 +410,6 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind {
412410
; RV64I-NEXT: addiw a1, a1, 1329
413411
; RV64I-NEXT: call __muldi3@plt
414412
; RV64I-NEXT: srliw a0, a0, 27
415-
; RV64I-NEXT: slli a0, a0, 32
416-
; RV64I-NEXT: srli a0, a0, 32
417413
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
418414
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_0)
419415
; RV64I-NEXT: add a0, a1, a0
@@ -443,8 +439,6 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
443439
; RV64I-NEXT: addiw a1, a1, 1329
444440
; RV64I-NEXT: call __muldi3@plt
445441
; RV64I-NEXT: srliw a0, a0, 27
446-
; RV64I-NEXT: slli a0, a0, 32
447-
; RV64I-NEXT: srli a0, a0, 32
448442
; RV64I-NEXT: lui a1, %hi(.LCPI8_0)
449443
; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0)
450444
; RV64I-NEXT: add a0, a1, a0
@@ -483,8 +477,6 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
483477
; RV64I-NEXT: addiw a1, a1, 1329
484478
; RV64I-NEXT: call __muldi3@plt
485479
; RV64I-NEXT: srliw a0, a0, 27
486-
; RV64I-NEXT: slli a0, a0, 32
487-
; RV64I-NEXT: srli a0, a0, 32
488480
; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
489481
; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
490482
; RV64I-NEXT: add a0, a1, a0

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -209,17 +209,13 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
209209
define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
210210
; RV64I-LABEL: packh_i16:
211211
; RV64I: # %bb.0:
212-
; RV64I-NEXT: slli a1, a1, 8
212+
; RV64I-NEXT: slliw a1, a1, 8
213213
; RV64I-NEXT: or a0, a1, a0
214-
; RV64I-NEXT: slli a0, a0, 32
215-
; RV64I-NEXT: srli a0, a0, 32
216214
; RV64I-NEXT: ret
217215
;
218216
; RV64ZBKB-LABEL: packh_i16:
219217
; RV64ZBKB: # %bb.0:
220218
; RV64ZBKB-NEXT: packh a0, a0, a1
221-
; RV64ZBKB-NEXT: slli a0, a0, 32
222-
; RV64ZBKB-NEXT: srli a0, a0, 32
223219
; RV64ZBKB-NEXT: ret
224220
%zext = zext i8 %a to i16
225221
%zext1 = zext i8 %b to i16

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