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fixup! [ModuloSchedule] Implement modulo variable expansion for pipelining
1 parent cf258e9 commit 921c493

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6 files changed

+34
-23
lines changed

6 files changed

+34
-23
lines changed

‎llvm/include/llvm/CodeGen/ModuloSchedule.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -408,9 +408,11 @@ class ModuloScheduleExpanderMVE {
408408
SmallVectorImpl<ValueMapTy> &KernelVRMap,
409409
SmallVectorImpl<ValueMapTy> &PhiVRMap);
410410
void generateKernel(SmallVectorImpl<ValueMapTy> &PrologVRMap,
411-
SmallVectorImpl<ValueMapTy> &KernelVRMap);
411+
SmallVectorImpl<ValueMapTy> &KernelVRMap,
412+
InstrMapTy &LastStage0Insts);
412413
void generateEpilog(SmallVectorImpl<ValueMapTy> &KernelVRMap,
413-
SmallVectorImpl<ValueMapTy> &EpilogVRMap);
414+
SmallVectorImpl<ValueMapTy> &EpilogVRMap,
415+
InstrMapTy &LastStage0Insts);
414416
void mergeRegUsesAfterPipeline(Register OrigReg, Register NewReg);
415417

416418
MachineInstr *cloneInstr(MachineInstr *OldMI);

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -768,15 +768,18 @@ class TargetInstrInfo : public MCInstrInfo {
768768
/// Create a condition to determine if the remaining trip count for a phase
769769
/// is greater than TC. Some instructions such as comparisons may be
770770
/// inserted at the bottom of MBB. The all instructions expanded for the
771-
/// phase must be inserted in MBB before calling this function. RegMap is
772-
/// the map from the original registers to the expanded registers for the
773-
/// phase.
771+
/// phase must be inserted in MBB before calling this function.
772+
/// LastStage0Insts is the map from the original instructions scheduled at
773+
/// stage#0 to the expanded instructions for the last iteration of the
774+
/// kernel. LastStage0Insts is intended to obtain the instruction that
775+
/// refers the latest loop counter value.
774776
///
775-
/// MBB can also be a predecessor of the prologue block. Then RegMap must be
776-
/// empty and the compared value is the initial value of the trip count.
777+
/// MBB can also be a predecessor of the prologue block. Then
778+
/// LastStage0Insts must be empty and the compared value is the initial
779+
/// value of the trip count.
777780
virtual void createRemainingIterationsGreaterCondition(
778781
int TC, MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &Cond,
779-
DenseMap<unsigned, unsigned> RegMap) = 0;
782+
DenseMap<MachineInstr *, MachineInstr *> LastStage0Insts) = 0;
780783

781784
/// Modify the loop such that the trip count is
782785
/// OriginalTC + TripCountAdjust.

‎llvm/lib/CodeGen/ModuloSchedule.cpp

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2263,15 +2263,16 @@ void ModuloScheduleExpanderMVE::generatePipelinedLoop() {
22632263

22642264
SmallVector<MachineOperand, 4> Cond;
22652265
LoopInfo->createRemainingIterationsGreaterCondition(
2266-
Schedule.getNumStages() + NumUnroll - 2, *Check, Cond, ValueMapTy());
2266+
Schedule.getNumStages() + NumUnroll - 2, *Check, Cond, InstrMapTy());
22672267
TII->insertBranch(*Check, Prolog, NewPreheader, Cond, DebugLoc());
22682268

22692269
// VRMaps map (prolog/kernel/epilog phase#, original register#) to new
22702270
// register#
22712271
SmallVector<ValueMapTy> PrologVRMap, KernelVRMap, EpilogVRMap;
2272+
InstrMapTy LastStage0Insts;
22722273
generateProlog(PrologVRMap);
2273-
generateKernel(PrologVRMap, KernelVRMap);
2274-
generateEpilog(KernelVRMap, EpilogVRMap);
2274+
generateKernel(PrologVRMap, KernelVRMap, LastStage0Insts);
2275+
generateEpilog(KernelVRMap, EpilogVRMap, LastStage0Insts);
22752276
}
22762277

22772278
/// Replace MI's use operands according to the maps.
@@ -2522,18 +2523,21 @@ void ModuloScheduleExpanderMVE::generateProlog(
25222523

25232524
void ModuloScheduleExpanderMVE::generateKernel(
25242525
SmallVectorImpl<ValueMapTy> &PrologVRMap,
2525-
SmallVectorImpl<ValueMapTy> &KernelVRMap) {
2526+
SmallVectorImpl<ValueMapTy> &KernelVRMap, InstrMapTy &LastStage0Insts) {
25262527
KernelVRMap.clear();
25272528
KernelVRMap.resize(NumUnroll);
25282529
SmallVector<ValueMapTy> PhiVRMap;
25292530
PhiVRMap.resize(NumUnroll);
25302531
DenseMap<MachineInstr *, std::pair<int, int>> NewMIMap;
2532+
DenseMap<MachineInstr *, MachineInstr *> MIMapLastStage0;
25312533
for (int UnrollNum = 0; UnrollNum < NumUnroll; ++UnrollNum) {
25322534
for (MachineInstr *MI : Schedule.getInstructions()) {
25332535
if (MI->isPHI())
25342536
continue;
25352537
int StageNum = Schedule.getStage(MI);
25362538
MachineInstr *NewMI = cloneInstr(MI);
2539+
if (UnrollNum == NumUnroll - 1)
2540+
LastStage0Insts[MI] = NewMI;
25372541
updateInstrDef(NewMI, KernelVRMap[UnrollNum],
25382542
(UnrollNum == NumUnroll - 1 && StageNum == 0));
25392543
generatePhi(MI, UnrollNum, PrologVRMap, KernelVRMap, PhiVRMap);
@@ -2551,8 +2555,8 @@ void ModuloScheduleExpanderMVE::generateKernel(
25512555

25522556
// If remaining trip count is greater than NumUnroll-1, loop continues
25532557
SmallVector<MachineOperand, 4> Cond;
2554-
LoopInfo->createRemainingIterationsGreaterCondition(
2555-
NumUnroll - 1, *NewKernel, Cond, KernelVRMap[NumUnroll - 1]);
2558+
LoopInfo->createRemainingIterationsGreaterCondition(NumUnroll - 1, *NewKernel,
2559+
Cond, LastStage0Insts);
25562560
TII->insertBranch(*NewKernel, NewKernel, Epilog, Cond, DebugLoc());
25572561

25582562
LLVM_DEBUG({
@@ -2563,7 +2567,7 @@ void ModuloScheduleExpanderMVE::generateKernel(
25632567

25642568
void ModuloScheduleExpanderMVE::generateEpilog(
25652569
SmallVectorImpl<ValueMapTy> &KernelVRMap,
2566-
SmallVectorImpl<ValueMapTy> &EpilogVRMap) {
2570+
SmallVectorImpl<ValueMapTy> &EpilogVRMap, InstrMapTy &LastStage0Insts) {
25672571
EpilogVRMap.clear();
25682572
EpilogVRMap.resize(Schedule.getNumStages() - 1);
25692573
DenseMap<MachineInstr *, std::pair<int, int>> NewMIMap;
@@ -2594,8 +2598,8 @@ void ModuloScheduleExpanderMVE::generateEpilog(
25942598
// are indicated by shouldIgnoreForPipelining() and are assumed to be placed
25952599
// in stage 0. Thus, the map is for the last one in the kernel.
25962600
SmallVector<MachineOperand, 4> Cond;
2597-
LoopInfo->createRemainingIterationsGreaterCondition(
2598-
0, *Epilog, Cond, KernelVRMap[NumUnroll - 1]);
2601+
LoopInfo->createRemainingIterationsGreaterCondition(0, *Epilog, Cond,
2602+
LastStage0Insts);
25992603
TII->insertBranch(*Epilog, NewPreheader, NewExit, Cond, DebugLoc());
26002604

26012605
LLVM_DEBUG({
@@ -2670,7 +2674,8 @@ void ModuloScheduleExpanderMVE::expand() {
26702674
/// Check if ModuloScheduleExpanderMVE can be applied to L
26712675
bool ModuloScheduleExpanderMVE::canApply(MachineLoop &L) {
26722676
if (!L.getExitBlock()) {
2673-
LLVM_DEBUG(dbgs() << "Can not apply MVE expander: No single exit block.\n";);
2677+
LLVM_DEBUG(
2678+
dbgs() << "Can not apply MVE expander: No single exit block.\n";);
26742679
return false;
26752680
}
26762681

@@ -2687,8 +2692,9 @@ bool ModuloScheduleExpanderMVE::canApply(MachineLoop &L) {
26872692
if (MO.isReg())
26882693
for (MachineInstr &Ref : MRI.use_instructions(MO.getReg()))
26892694
if (Ref.getParent() != BB || Ref.isPHI()) {
2690-
LLVM_DEBUG(dbgs() << "Can not apply MVE expander: A phi result is "
2691-
"referenced outside of the loop or by phi.\n";);
2695+
LLVM_DEBUG(dbgs()
2696+
<< "Can not apply MVE expander: A phi result is "
2697+
"referenced outside of the loop or by phi.\n";);
26922698
return false;
26932699
}
26942700

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6825,7 +6825,7 @@ class ARMPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
68256825

68266826
void createRemainingIterationsGreaterCondition(
68276827
int TC, MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &Cond,
6828-
DenseMap<unsigned, unsigned> RegMap) override {
6828+
DenseMap<MachineInstr *, MachineInstr *> LastStage0Insts) override {
68296829
llvm_unreachable(
68306830
"Target didn't implement createRemainingIterationsGreaterCondition");
68316831
}

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -772,7 +772,7 @@ class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
772772

773773
void createRemainingIterationsGreaterCondition(
774774
int TC, MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &Cond,
775-
DenseMap<unsigned, unsigned> RegMap) override {
775+
DenseMap<MachineInstr *, MachineInstr *> LastStage0Insts) override {
776776
llvm_unreachable(
777777
"Target didn't implement createRemainingIterationsGreaterCondition");
778778
}

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5441,7 +5441,7 @@ class PPCPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
54415441

54425442
void createRemainingIterationsGreaterCondition(
54435443
int TC, MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &Cond,
5444-
DenseMap<unsigned, unsigned> RegMap) override {
5444+
DenseMap<MachineInstr *, MachineInstr *> LastStage0Insts) override {
54455445
llvm_unreachable(
54465446
"Target didn't implement createRemainingIterationsGreaterCondition");
54475447
}

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