@@ -1744,7 +1744,8 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
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bool IsStrict = Node->isStrictFPOpcode ();
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unsigned OpNo = IsStrict ? 1 : 0 ;
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SDValue Src = Node->getOperand (OpNo);
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- EVT VT = Src.getValueType ();
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+ EVT SrcVT = Src.getValueType ();
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+ EVT DstVT = Node->getValueType (0 );
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SDLoc DL (Node);
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// Attempt to expand using TargetLowering.
@@ -1758,11 +1759,11 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
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}
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// Make sure that the SINT_TO_FP and SRL instructions are available.
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- if (((!IsStrict && TLI.getOperationAction (ISD::SINT_TO_FP, VT ) ==
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+ if (((!IsStrict && TLI.getOperationAction (ISD::SINT_TO_FP, SrcVT ) ==
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TargetLowering::Expand) ||
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- (IsStrict && TLI.getOperationAction (ISD::STRICT_SINT_TO_FP, VT ) ==
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+ (IsStrict && TLI.getOperationAction (ISD::STRICT_SINT_TO_FP, SrcVT ) ==
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TargetLowering::Expand)) ||
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- TLI.getOperationAction (ISD::SRL, VT ) == TargetLowering::Expand) {
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+ TLI.getOperationAction (ISD::SRL, SrcVT ) == TargetLowering::Expand) {
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if (IsStrict) {
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UnrollStrictFPOp (Node, Results);
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return ;
@@ -1772,46 +1773,42 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
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return ;
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}
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- unsigned BW = VT .getScalarSizeInBits ();
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+ unsigned BW = SrcVT .getScalarSizeInBits ();
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assert ((BW == 64 || BW == 32 ) &&
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" Elements in vector-UINT_TO_FP must be 32 or 64 bits wide" );
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- SDValue HalfWord = DAG.getConstant (BW / 2 , DL, VT );
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+ SDValue HalfWord = DAG.getConstant (BW / 2 , DL, SrcVT );
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// Constants to clear the upper part of the word.
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// Notice that we can also use SHL+SHR, but using a constant is slightly
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// faster on x86.
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uint64_t HWMask = (BW == 64 ) ? 0x00000000FFFFFFFF : 0x0000FFFF ;
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- SDValue HalfWordMask = DAG.getConstant (HWMask, DL, VT );
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+ SDValue HalfWordMask = DAG.getConstant (HWMask, DL, SrcVT );
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// Two to the power of half-word-size.
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- SDValue TWOHW =
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- DAG.getConstantFP (1ULL << (BW / 2 ), DL, Node->getValueType (0 ));
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+ SDValue TWOHW = DAG.getConstantFP (1ULL << (BW / 2 ), DL, DstVT);
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// Clear upper part of LO, lower HI
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- SDValue HI = DAG.getNode (ISD::SRL, DL, VT , Src, HalfWord);
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- SDValue LO = DAG.getNode (ISD::AND, DL, VT , Src, HalfWordMask);
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+ SDValue HI = DAG.getNode (ISD::SRL, DL, SrcVT , Src, HalfWord);
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+ SDValue LO = DAG.getNode (ISD::AND, DL, SrcVT , Src, HalfWordMask);
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if (IsStrict) {
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// Convert hi and lo to floats
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// Convert the hi part back to the upper values
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// TODO: Can any fast-math-flags be set on these nodes?
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- SDValue fHI = DAG.getNode (ISD::STRICT_SINT_TO_FP, DL,
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- {Node->getValueType (0 ), MVT::Other},
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+ SDValue fHI = DAG.getNode (ISD::STRICT_SINT_TO_FP, DL, {DstVT, MVT::Other},
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{Node->getOperand (0 ), HI});
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- fHI = DAG.getNode (ISD::STRICT_FMUL, DL, {Node-> getValueType ( 0 ) , MVT::Other},
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+ fHI = DAG.getNode (ISD::STRICT_FMUL, DL, {DstVT , MVT::Other},
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{fHI .getValue (1 ), fHI , TWOHW});
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- SDValue fLO = DAG.getNode (ISD::STRICT_SINT_TO_FP, DL,
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- {Node->getValueType (0 ), MVT::Other},
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+ SDValue fLO = DAG.getNode (ISD::STRICT_SINT_TO_FP, DL, {DstVT, MVT::Other},
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{Node->getOperand (0 ), LO});
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SDValue TF = DAG.getNode (ISD::TokenFactor, DL, MVT::Other, fHI .getValue (1 ),
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fLO .getValue (1 ));
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// Add the two halves
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SDValue Result =
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- DAG.getNode (ISD::STRICT_FADD, DL, {Node->getValueType (0 ), MVT::Other},
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- {TF, fHI , fLO });
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+ DAG.getNode (ISD::STRICT_FADD, DL, {DstVT, MVT::Other}, {TF, fHI , fLO });
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Results.push_back (Result);
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Results.push_back (Result.getValue (1 ));
@@ -1821,13 +1818,12 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
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// Convert hi and lo to floats
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// Convert the hi part back to the upper values
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// TODO: Can any fast-math-flags be set on these nodes?
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- SDValue fHI = DAG.getNode (ISD::SINT_TO_FP, DL, Node-> getValueType ( 0 ) , HI);
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- fHI = DAG.getNode (ISD::FMUL, DL, Node-> getValueType ( 0 ) , fHI , TWOHW);
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- SDValue fLO = DAG.getNode (ISD::SINT_TO_FP, DL, Node-> getValueType ( 0 ) , LO);
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+ SDValue fHI = DAG.getNode (ISD::SINT_TO_FP, DL, DstVT , HI);
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+ fHI = DAG.getNode (ISD::FMUL, DL, DstVT , fHI , TWOHW);
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+ SDValue fLO = DAG.getNode (ISD::SINT_TO_FP, DL, DstVT , LO);
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// Add the two halves
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- Results.push_back (
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- DAG.getNode (ISD::FADD, DL, Node->getValueType (0 ), fHI , fLO ));
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+ Results.push_back (DAG.getNode (ISD::FADD, DL, DstVT, fHI , fLO ));
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}
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SDValue VectorLegalizer::ExpandFNEG (SDNode *Node) {
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