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[DAG] VectorLegalizer::ExpandUINT_TO_FLOAT- pull out repeated getValueType calls. NFC.
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llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 19 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1744,7 +1744,8 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
17441744
bool IsStrict = Node->isStrictFPOpcode();
17451745
unsigned OpNo = IsStrict ? 1 : 0;
17461746
SDValue Src = Node->getOperand(OpNo);
1747-
EVT VT = Src.getValueType();
1747+
EVT SrcVT = Src.getValueType();
1748+
EVT DstVT = Node->getValueType(0);
17481749
SDLoc DL(Node);
17491750

17501751
// Attempt to expand using TargetLowering.
@@ -1758,11 +1759,11 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
17581759
}
17591760

17601761
// Make sure that the SINT_TO_FP and SRL instructions are available.
1761-
if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, VT) ==
1762+
if (((!IsStrict && TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) ==
17621763
TargetLowering::Expand) ||
1763-
(IsStrict && TLI.getOperationAction(ISD::STRICT_SINT_TO_FP, VT) ==
1764+
(IsStrict && TLI.getOperationAction(ISD::STRICT_SINT_TO_FP, SrcVT) ==
17641765
TargetLowering::Expand)) ||
1765-
TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) {
1766+
TLI.getOperationAction(ISD::SRL, SrcVT) == TargetLowering::Expand) {
17661767
if (IsStrict) {
17671768
UnrollStrictFPOp(Node, Results);
17681769
return;
@@ -1772,46 +1773,42 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
17721773
return;
17731774
}
17741775

1775-
unsigned BW = VT.getScalarSizeInBits();
1776+
unsigned BW = SrcVT.getScalarSizeInBits();
17761777
assert((BW == 64 || BW == 32) &&
17771778
"Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
17781779

1779-
SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
1780+
SDValue HalfWord = DAG.getConstant(BW / 2, DL, SrcVT);
17801781

17811782
// Constants to clear the upper part of the word.
17821783
// Notice that we can also use SHL+SHR, but using a constant is slightly
17831784
// faster on x86.
17841785
uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
1785-
SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1786+
SDValue HalfWordMask = DAG.getConstant(HWMask, DL, SrcVT);
17861787

17871788
// Two to the power of half-word-size.
1788-
SDValue TWOHW =
1789-
DAG.getConstantFP(1ULL << (BW / 2), DL, Node->getValueType(0));
1789+
SDValue TWOHW = DAG.getConstantFP(1ULL << (BW / 2), DL, DstVT);
17901790

17911791
// Clear upper part of LO, lower HI
1792-
SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Src, HalfWord);
1793-
SDValue LO = DAG.getNode(ISD::AND, DL, VT, Src, HalfWordMask);
1792+
SDValue HI = DAG.getNode(ISD::SRL, DL, SrcVT, Src, HalfWord);
1793+
SDValue LO = DAG.getNode(ISD::AND, DL, SrcVT, Src, HalfWordMask);
17941794

17951795
if (IsStrict) {
17961796
// Convert hi and lo to floats
17971797
// Convert the hi part back to the upper values
17981798
// TODO: Can any fast-math-flags be set on these nodes?
1799-
SDValue fHI = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL,
1800-
{Node->getValueType(0), MVT::Other},
1799+
SDValue fHI = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL, {DstVT, MVT::Other},
18011800
{Node->getOperand(0), HI});
1802-
fHI = DAG.getNode(ISD::STRICT_FMUL, DL, {Node->getValueType(0), MVT::Other},
1801+
fHI = DAG.getNode(ISD::STRICT_FMUL, DL, {DstVT, MVT::Other},
18031802
{fHI.getValue(1), fHI, TWOHW});
1804-
SDValue fLO = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL,
1805-
{Node->getValueType(0), MVT::Other},
1803+
SDValue fLO = DAG.getNode(ISD::STRICT_SINT_TO_FP, DL, {DstVT, MVT::Other},
18061804
{Node->getOperand(0), LO});
18071805

18081806
SDValue TF = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, fHI.getValue(1),
18091807
fLO.getValue(1));
18101808

18111809
// Add the two halves
18121810
SDValue Result =
1813-
DAG.getNode(ISD::STRICT_FADD, DL, {Node->getValueType(0), MVT::Other},
1814-
{TF, fHI, fLO});
1811+
DAG.getNode(ISD::STRICT_FADD, DL, {DstVT, MVT::Other}, {TF, fHI, fLO});
18151812

18161813
Results.push_back(Result);
18171814
Results.push_back(Result.getValue(1));
@@ -1821,13 +1818,12 @@ void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,
18211818
// Convert hi and lo to floats
18221819
// Convert the hi part back to the upper values
18231820
// TODO: Can any fast-math-flags be set on these nodes?
1824-
SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), HI);
1825-
fHI = DAG.getNode(ISD::FMUL, DL, Node->getValueType(0), fHI, TWOHW);
1826-
SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Node->getValueType(0), LO);
1821+
SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, DstVT, HI);
1822+
fHI = DAG.getNode(ISD::FMUL, DL, DstVT, fHI, TWOHW);
1823+
SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, DstVT, LO);
18271824

18281825
// Add the two halves
1829-
Results.push_back(
1830-
DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO));
1826+
Results.push_back(DAG.getNode(ISD::FADD, DL, DstVT, fHI, fLO));
18311827
}
18321828

18331829
SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {

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