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MalaySanghie-kud
MalaySanghi
and
e-kud
authored
[X86][GISel] Add DU chain lookups for LOAD & STORE (#87453)
For G_LOAD and G_STORE we want this information during regbankselect. Today we treat load dest as integer and insert converts. --------- Co-authored-by: Evgenii Kudriashov <[email protected]>
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11 files changed

+367
-171
lines changed

11 files changed

+367
-171
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/Utils.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -555,5 +555,9 @@ void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI,
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/// debug users of \p MI by writing the effect of \p MI in a DIExpression.
556556
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI);
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558+
/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
559+
/// having only floating-point operands.
560+
bool isPreISelGenericFloatingPointOpcode(unsigned Opc);
561+
558562
} // End namespace llvm.
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#endif

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp

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@@ -1665,3 +1665,47 @@ void llvm::salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI) {
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}
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}
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}
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bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
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switch (Opc) {
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case TargetOpcode::G_FABS:
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case TargetOpcode::G_FADD:
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case TargetOpcode::G_FCANONICALIZE:
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case TargetOpcode::G_FCEIL:
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case TargetOpcode::G_FCONSTANT:
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case TargetOpcode::G_FCOPYSIGN:
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case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_FEXP2:
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case TargetOpcode::G_FEXP:
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case TargetOpcode::G_FFLOOR:
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case TargetOpcode::G_FLOG10:
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case TargetOpcode::G_FLOG2:
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case TargetOpcode::G_FLOG:
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case TargetOpcode::G_FMA:
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case TargetOpcode::G_FMAD:
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case TargetOpcode::G_FMAXIMUM:
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case TargetOpcode::G_FMAXNUM:
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case TargetOpcode::G_FMAXNUM_IEEE:
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case TargetOpcode::G_FMINIMUM:
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case TargetOpcode::G_FMINNUM:
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case TargetOpcode::G_FMINNUM_IEEE:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FNEARBYINT:
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case TargetOpcode::G_FNEG:
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case TargetOpcode::G_FPEXT:
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case TargetOpcode::G_FPOW:
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case TargetOpcode::G_FPTRUNC:
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case TargetOpcode::G_FREM:
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case TargetOpcode::G_FRINT:
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case TargetOpcode::G_FSIN:
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case TargetOpcode::G_FSQRT:
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case TargetOpcode::G_FSUB:
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case TargetOpcode::G_INTRINSIC_ROUND:
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case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
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case TargetOpcode::G_INTRINSIC_TRUNC:
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return true;
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default:
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return false;
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}
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}

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 0 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -424,43 +424,6 @@ void AArch64RegisterBankInfo::applyMappingImpl(
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}
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}
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427-
/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
428-
/// having only floating-point operands.
429-
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
430-
switch (Opc) {
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case TargetOpcode::G_FADD:
432-
case TargetOpcode::G_FSUB:
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case TargetOpcode::G_FMUL:
434-
case TargetOpcode::G_FMA:
435-
case TargetOpcode::G_FDIV:
436-
case TargetOpcode::G_FCONSTANT:
437-
case TargetOpcode::G_FPEXT:
438-
case TargetOpcode::G_FPTRUNC:
439-
case TargetOpcode::G_FCEIL:
440-
case TargetOpcode::G_FFLOOR:
441-
case TargetOpcode::G_FNEARBYINT:
442-
case TargetOpcode::G_FNEG:
443-
case TargetOpcode::G_FCOS:
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case TargetOpcode::G_FSIN:
445-
case TargetOpcode::G_FLOG10:
446-
case TargetOpcode::G_FLOG:
447-
case TargetOpcode::G_FLOG2:
448-
case TargetOpcode::G_FSQRT:
449-
case TargetOpcode::G_FABS:
450-
case TargetOpcode::G_FEXP:
451-
case TargetOpcode::G_FRINT:
452-
case TargetOpcode::G_INTRINSIC_TRUNC:
453-
case TargetOpcode::G_INTRINSIC_ROUND:
454-
case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
455-
case TargetOpcode::G_FMAXNUM:
456-
case TargetOpcode::G_FMINNUM:
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case TargetOpcode::G_FMAXIMUM:
458-
case TargetOpcode::G_FMINIMUM:
459-
return true;
460-
}
461-
return false;
462-
}
463-
464427
const RegisterBankInfo::InstructionMapping &
465428
AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
466429
const MachineInstr &MI) const {

‎llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

Lines changed: 2 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -104,26 +104,6 @@ MipsRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
104104
}
105105
}
106106

107-
// Instructions where all register operands are floating point.
108-
static bool isFloatingPointOpcode(unsigned Opc) {
109-
switch (Opc) {
110-
case TargetOpcode::G_FCONSTANT:
111-
case TargetOpcode::G_FADD:
112-
case TargetOpcode::G_FSUB:
113-
case TargetOpcode::G_FMUL:
114-
case TargetOpcode::G_FDIV:
115-
case TargetOpcode::G_FABS:
116-
case TargetOpcode::G_FSQRT:
117-
case TargetOpcode::G_FCEIL:
118-
case TargetOpcode::G_FFLOOR:
119-
case TargetOpcode::G_FPEXT:
120-
case TargetOpcode::G_FPTRUNC:
121-
return true;
122-
default:
123-
return false;
124-
}
125-
}
126-
127107
// Instructions where use operands are floating point registers.
128108
// Def operands are general purpose.
129109
static bool isFloatingPointOpcodeUse(unsigned Opc) {
@@ -133,7 +113,7 @@ static bool isFloatingPointOpcodeUse(unsigned Opc) {
133113
case TargetOpcode::G_FCMP:
134114
return true;
135115
default:
136-
return isFloatingPointOpcode(Opc);
116+
return isPreISelGenericFloatingPointOpcode(Opc);
137117
}
138118
}
139119

@@ -145,7 +125,7 @@ static bool isFloatingPointOpcodeDef(unsigned Opc) {
145125
case TargetOpcode::G_UITOFP:
146126
return true;
147127
default:
148-
return isFloatingPointOpcode(Opc);
128+
return isPreISelGenericFloatingPointOpcode(Opc);
149129
}
150130
}
151131

‎llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp

Lines changed: 1 addition & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include "PPCRegisterBankInfo.h"
1414
#include "PPCRegisterInfo.h"
1515
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
16+
#include "llvm/CodeGen/GlobalISel/Utils.h"
1617
#include "llvm/CodeGen/MachineFunction.h"
1718
#include "llvm/CodeGen/MachineRegisterInfo.h"
1819
#include "llvm/Support/Debug.h"
@@ -239,44 +240,6 @@ PPCRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
239240
return getInstructionMapping(MappingID, Cost, OperandsMapping, NumOperands);
240241
}
241242

242-
/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
243-
/// having only floating-point operands.
244-
/// FIXME: this is copied from target AArch64. Needs some code refactor here to
245-
/// put this function in GlobalISel/Utils.cpp.
246-
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
247-
switch (Opc) {
248-
case TargetOpcode::G_FADD:
249-
case TargetOpcode::G_FSUB:
250-
case TargetOpcode::G_FMUL:
251-
case TargetOpcode::G_FMA:
252-
case TargetOpcode::G_FDIV:
253-
case TargetOpcode::G_FCONSTANT:
254-
case TargetOpcode::G_FPEXT:
255-
case TargetOpcode::G_FPTRUNC:
256-
case TargetOpcode::G_FCEIL:
257-
case TargetOpcode::G_FFLOOR:
258-
case TargetOpcode::G_FNEARBYINT:
259-
case TargetOpcode::G_FNEG:
260-
case TargetOpcode::G_FCOS:
261-
case TargetOpcode::G_FSIN:
262-
case TargetOpcode::G_FLOG10:
263-
case TargetOpcode::G_FLOG:
264-
case TargetOpcode::G_FLOG2:
265-
case TargetOpcode::G_FSQRT:
266-
case TargetOpcode::G_FABS:
267-
case TargetOpcode::G_FEXP:
268-
case TargetOpcode::G_FRINT:
269-
case TargetOpcode::G_INTRINSIC_TRUNC:
270-
case TargetOpcode::G_INTRINSIC_ROUND:
271-
case TargetOpcode::G_FMAXNUM:
272-
case TargetOpcode::G_FMINNUM:
273-
case TargetOpcode::G_FMAXIMUM:
274-
case TargetOpcode::G_FMINIMUM:
275-
return true;
276-
}
277-
return false;
278-
}
279-
280243
/// \returns true if a given intrinsic \p ID only uses and defines FPRs.
281244
static bool isFPIntrinsic(unsigned ID) {
282245
// TODO: Add more intrinsics.

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 0 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -154,46 +154,6 @@ static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
154154
return &RISCV::ValueMappings[Idx];
155155
}
156156

157-
/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
158-
/// having only floating-point operands.
159-
/// FIXME: this is copied from target AArch64. Needs some code refactor here to
160-
/// put this function in GlobalISel/Utils.cpp.
161-
static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
162-
switch (Opc) {
163-
case TargetOpcode::G_FADD:
164-
case TargetOpcode::G_FSUB:
165-
case TargetOpcode::G_FMUL:
166-
case TargetOpcode::G_FMA:
167-
case TargetOpcode::G_FDIV:
168-
case TargetOpcode::G_FCONSTANT:
169-
case TargetOpcode::G_FPEXT:
170-
case TargetOpcode::G_FPTRUNC:
171-
case TargetOpcode::G_FCEIL:
172-
case TargetOpcode::G_FFLOOR:
173-
case TargetOpcode::G_FNEARBYINT:
174-
case TargetOpcode::G_FNEG:
175-
case TargetOpcode::G_FCOPYSIGN:
176-
case TargetOpcode::G_FCOS:
177-
case TargetOpcode::G_FSIN:
178-
case TargetOpcode::G_FLOG10:
179-
case TargetOpcode::G_FLOG:
180-
case TargetOpcode::G_FLOG2:
181-
case TargetOpcode::G_FSQRT:
182-
case TargetOpcode::G_FABS:
183-
case TargetOpcode::G_FEXP:
184-
case TargetOpcode::G_FRINT:
185-
case TargetOpcode::G_INTRINSIC_TRUNC:
186-
case TargetOpcode::G_INTRINSIC_ROUND:
187-
case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
188-
case TargetOpcode::G_FMAXNUM:
189-
case TargetOpcode::G_FMINNUM:
190-
case TargetOpcode::G_FMAXIMUM:
191-
case TargetOpcode::G_FMINIMUM:
192-
return true;
193-
}
194-
return false;
195-
}
196-
197157
// TODO: Make this more like AArch64?
198158
bool RISCVRegisterBankInfo::hasFPConstraints(
199159
const MachineInstr &MI, const MachineRegisterInfo &MRI,

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