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[RISCV][NFCI] Fix Xqci Line Endings
Changes the new files for `Xqci`, including `Xqcicsr` and `Xqcisls`, to use Unix line endings rather than Windows line endings.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 74 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -1,74 +1,74 @@
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//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the vendor extensions defined by QUALCOMM.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
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class QCILoad_ScaleIdx<bits<4> func4, string opcodestr>
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: RVInstRBase<0b111, OPC_CUSTOM_0,
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(outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
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opcodestr, "$rd, $rs1, $rs2, $shamt"> {
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bits<3> shamt;
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let Inst{31-28} = func4;
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let Inst{27-25} = shamt;
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}
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
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// rd corresponds to the source for the store 'rs3' described in the spec.
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class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
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: RVInstRBase<0b110, OPC_CUSTOM_1, (outs),
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(ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
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opcodestr, "$rd, $rs1, $rs2, $shamt"> {
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bits<3> shamt;
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let Inst{31-28} = func4;
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let Inst{27-25} = shamt;
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}
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd),
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(ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
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"$rd, $rs1, $rs2">;
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def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd),
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(ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri",
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"$rd, $rs1, $rs2">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr"
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let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in {
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def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">;
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def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">;
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def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">;
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def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">;
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def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">;
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def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">;
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def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">;
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def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">;
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} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls"
1+
//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the vendor extensions defined by QUALCOMM.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
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class QCILoad_ScaleIdx<bits<4> func4, string opcodestr>
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: RVInstRBase<0b111, OPC_CUSTOM_0,
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(outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
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opcodestr, "$rd, $rs1, $rs2, $shamt"> {
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bits<3> shamt;
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let Inst{31-28} = func4;
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let Inst{27-25} = shamt;
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}
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
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// rd corresponds to the source for the store 'rs3' described in the spec.
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class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
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: RVInstRBase<0b110, OPC_CUSTOM_1, (outs),
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(ins GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
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opcodestr, "$rd, $rs1, $rs2, $shamt"> {
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bits<3> shamt;
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let Inst{31-28} = func4;
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let Inst{27-25} = shamt;
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}
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd),
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(ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
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"$rd, $rs1, $rs2">;
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def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd),
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(ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri",
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"$rd, $rs1, $rs2">;
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} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr"
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let Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls" in {
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def QC_LRB : QCILoad_ScaleIdx<0b1000, "qc.lrb">;
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def QC_LRH : QCILoad_ScaleIdx<0b1001, "qc.lrh">;
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def QC_LRW : QCILoad_ScaleIdx<0b1010, "qc.lrw">;
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def QC_LRBU : QCILoad_ScaleIdx<0b1011, "qc.lrbu">;
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def QC_LRHU : QCILoad_ScaleIdx<0b1100, "qc.lrhu">;
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def QC_SRB : QCIStore_ScaleIdx<0b1101, "qc.srb">;
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def QC_SRH : QCIStore_ScaleIdx<0b1110, "qc.srh">;
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def QC_SRW : QCIStore_ScaleIdx<0b1111, "qc.srw">;
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} // Predicates = [HasVendorXqcisls, IsRV32], DecoderNamespace = "Xqcisls"

‎llvm/test/MC/RISCV/xqcicsr-invalid.s

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,27 @@
1-
# Xqcicsr - Qualcomm uC CSR Extension
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicsr < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
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# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
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# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
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qc.csrrwr x10, x5, x0
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.csrrwr x10, x5
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
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qc.csrrwr x10, x5, x20
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# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
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qc.csrrwri x20, 31, x0
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# CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be an integer in the range [0, 31]
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qc.csrrwri x20, 45, x12
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.csrrwri x20, 23
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
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qc.csrrwri x30, 31, x12
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# Xqcicsr - Qualcomm uC CSR Extension
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicsr < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
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# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
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# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
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qc.csrrwr x10, x5, x0
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.csrrwr x10, x5
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
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qc.csrrwr x10, x5, x20
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# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
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qc.csrrwri x20, 31, x0
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# CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be an integer in the range [0, 31]
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qc.csrrwri x20, 45, x12
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.csrrwri x20, 23
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
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qc.csrrwri x30, 31, x12

‎llvm/test/MC/RISCV/xqcicsr-valid.s

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,19 @@
1-
# Xqcicsr - Qualcomm uC CSR Extension
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xqcicsr -M no-aliases --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xqcicsr --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: qc.csrrwr a0, t0, s4
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# CHECK-ENC: encoding: [0x73,0x85,0x42,0x8d]
15-
qc.csrrwr x10, x5, x20
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# CHECK-INST: qc.csrrwri s4, 31, a2
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# CHECK-ENC: encoding: [0x73,0x8a,0xcf,0x8e]
19-
qc.csrrwri x20, 31, x12
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# Xqcicsr - Qualcomm uC CSR Extension
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xqcicsr -M no-aliases --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
10+
# RUN: | llvm-objdump --mattr=+experimental-xqcicsr --no-print-imm-hex -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
12+
13+
# CHECK-INST: qc.csrrwr a0, t0, s4
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# CHECK-ENC: encoding: [0x73,0x85,0x42,0x8d]
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qc.csrrwr x10, x5, x20
16+
17+
# CHECK-INST: qc.csrrwri s4, 31, a2
18+
# CHECK-ENC: encoding: [0x73,0x8a,0xcf,0x8e]
19+
qc.csrrwri x20, 31, x12

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