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[AMDGPU][NFC] Add True16 operand definitions.
Reviewed By: Joe_Nash Differential Revision: https://reviews.llvm.org/D156103
1 parent dae7e2d commit 9310baa

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11 files changed

+257
-29
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11 files changed

+257
-29
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‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -273,6 +273,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
273273
return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);
274274
}
275275

276+
bool isRegOrImmWithIntT16InputMods() const {
277+
return isRegOrImmWithInputMods(AMDGPU::VS_16RegClassID, MVT::i16);
278+
}
279+
276280
bool isRegOrImmWithInt32InputMods() const {
277281
return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);
278282
}
@@ -293,6 +297,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
293297
return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);
294298
}
295299

300+
bool isRegOrImmWithFPT16InputMods() const {
301+
return isRegOrImmWithInputMods(AMDGPU::VS_16RegClassID, MVT::f16);
302+
}
303+
296304
bool isRegOrImmWithFP32InputMods() const {
297305
return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);
298306
}
@@ -512,7 +520,15 @@ class AMDGPUOperand : public MCParsedAsmOperand {
512520
return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);
513521
}
514522

523+
bool isVCSrcTB16() const {
524+
return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::i16);
525+
}
526+
515527
bool isVCSrcTB16_Lo128() const {
528+
return isRegOrInlineNoMods(AMDGPU::VS_16_Lo128RegClassID, MVT::i16);
529+
}
530+
531+
bool isVCSrcFake16B16_Lo128() const {
516532
return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::i16);
517533
}
518534

@@ -532,7 +548,15 @@ class AMDGPUOperand : public MCParsedAsmOperand {
532548
return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
533549
}
534550

551+
bool isVCSrcTF16() const {
552+
return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::f16);
553+
}
554+
535555
bool isVCSrcTF16_Lo128() const {
556+
return isRegOrInlineNoMods(AMDGPU::VS_16_Lo128RegClassID, MVT::f16);
557+
}
558+
559+
bool isVCSrcFake16F16_Lo128() const {
536560
return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::f16);
537561
}
538562

@@ -552,10 +576,16 @@ class AMDGPUOperand : public MCParsedAsmOperand {
552576
return isVCSrcF64() || isLiteralImm(MVT::i64);
553577
}
554578

579+
bool isVSrcTB16() const { return isVCSrcTB16() || isLiteralImm(MVT::i16); }
580+
555581
bool isVSrcTB16_Lo128() const {
556582
return isVCSrcTB16_Lo128() || isLiteralImm(MVT::i16);
557583
}
558584

585+
bool isVSrcFake16B16_Lo128() const {
586+
return isVCSrcFake16B16_Lo128() || isLiteralImm(MVT::i16);
587+
}
588+
559589
bool isVSrcB16() const {
560590
return isVCSrcB16() || isLiteralImm(MVT::i16);
561591
}
@@ -588,10 +618,16 @@ class AMDGPUOperand : public MCParsedAsmOperand {
588618
return isVCSrcF64() || isLiteralImm(MVT::f64);
589619
}
590620

621+
bool isVSrcTF16() const { return isVCSrcTF16() || isLiteralImm(MVT::f16); }
622+
591623
bool isVSrcTF16_Lo128() const {
592624
return isVCSrcTF16_Lo128() || isLiteralImm(MVT::f16);
593625
}
594626

627+
bool isVSrcFake16F16_Lo128() const {
628+
return isVCSrcFake16F16_Lo128() || isLiteralImm(MVT::f16);
629+
}
630+
595631
bool isVSrcF16() const {
596632
return isVCSrcF16() || isLiteralImm(MVT::f16);
597633
}

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,61 @@ DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16)
262262
DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32)
263263
DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32)
264264

265+
static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm,
266+
uint64_t /*Addr*/,
267+
const MCDisassembler *Decoder) {
268+
assert(isUInt<10>(Imm) && "10-bit encoding expected");
269+
assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used");
270+
271+
bool IsHi = Imm & (1 << 9);
272+
unsigned RegIdx = Imm & 0xff;
273+
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
274+
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
275+
}
276+
277+
static DecodeStatus
278+
DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,
279+
const MCDisassembler *Decoder) {
280+
assert(isUInt<8>(Imm) && "8-bit encoding expected");
281+
282+
bool IsHi = Imm & (1 << 7);
283+
unsigned RegIdx = Imm & 0x7f;
284+
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
285+
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
286+
}
287+
288+
static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
289+
uint64_t /*Addr*/,
290+
const MCDisassembler *Decoder) {
291+
assert(isUInt<9>(Imm) && "9-bit encoding expected");
292+
293+
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
294+
bool IsVGPR = Imm & (1 << 8);
295+
if (IsVGPR) {
296+
bool IsHi = Imm & (1 << 7);
297+
unsigned RegIdx = Imm & 0x7f;
298+
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
299+
}
300+
return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
301+
Imm & 0xFF, false, 16));
302+
}
303+
304+
static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
305+
uint64_t /*Addr*/,
306+
const MCDisassembler *Decoder) {
307+
assert(isUInt<10>(Imm) && "10-bit encoding expected");
308+
309+
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
310+
bool IsVGPR = Imm & (1 << 8);
311+
if (IsVGPR) {
312+
bool IsHi = Imm & (1 << 9);
313+
unsigned RegIdx = Imm & 0xff;
314+
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
315+
}
316+
return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
317+
Imm & 0xFF, false, 16));
318+
}
319+
265320
static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,
266321
uint64_t Addr,
267322
const MCDisassembler *Decoder) {
@@ -1141,6 +1196,13 @@ MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
11411196
return createRegOperand(SRegClassID, Val >> shift);
11421197
}
11431198

1199+
MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx,
1200+
bool IsHi) const {
1201+
unsigned RCID =
1202+
IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID;
1203+
return createRegOperand(RCID, RegIdx);
1204+
}
1205+
11441206
// Decode Literals for insts which always have a literal in the encoding
11451207
MCOperand
11461208
AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const {
@@ -1397,6 +1459,18 @@ MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val,
13971459
return createRegOperand(IsAGPR ? getAgprClassId(Width)
13981460
: getVgprClassId(Width), Val - VGPR_MIN);
13991461
}
1462+
return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth);
1463+
}
1464+
1465+
MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width,
1466+
unsigned Val,
1467+
bool MandatoryLiteral,
1468+
unsigned ImmWidth) const {
1469+
// Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been
1470+
// decoded earlier.
1471+
assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0");
1472+
using namespace AMDGPU::EncValues;
1473+
14001474
if (Val <= SGPR_MAX) {
14011475
// "SGPR_MIN <= Val" is always true and causes compilation warning.
14021476
static_assert(SGPR_MIN == 0);

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,7 @@ class AMDGPUDisassembler : public MCDisassembler {
114114
MCOperand createRegOperand(unsigned int RegId) const;
115115
MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
116116
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
117+
MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
117118

118119
MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
119120

@@ -234,6 +235,10 @@ class AMDGPUDisassembler : public MCDisassembler {
234235
bool MandatoryLiteral = false,
235236
unsigned ImmWidth = 0) const;
236237

238+
MCOperand decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val,
239+
bool MandatoryLiteral = false,
240+
unsigned ImmWidth = 0) const;
241+
237242
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
238243
MCOperand decodeSpecialReg32(unsigned Val) const;
239244
MCOperand decodeSpecialReg64(unsigned Val) const;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,14 @@ class AMDGPUMCCodeEmitter : public MCCodeEmitter {
4949
SmallVectorImpl<MCFixup> &Fixups,
5050
const MCSubtargetInfo &STI) const;
5151

52+
void getMachineOpValueT16(const MCInst &MI, unsigned OpNo, APInt &Op,
53+
SmallVectorImpl<MCFixup> &Fixups,
54+
const MCSubtargetInfo &STI) const;
55+
56+
void getMachineOpValueT16Lo128(const MCInst &MI, unsigned OpNo, APInt &Op,
57+
SmallVectorImpl<MCFixup> &Fixups,
58+
const MCSubtargetInfo &STI) const;
59+
5260
/// Use a fixup to encode the simm16 field for SOPP branch
5361
/// instructions.
5462
void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
@@ -547,6 +555,28 @@ void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI,
547555
getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
548556
}
549557

558+
void AMDGPUMCCodeEmitter::getMachineOpValueT16(
559+
const MCInst &MI, unsigned OpNo, APInt &Op,
560+
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
561+
llvm_unreachable("TODO: Implement getMachineOpValueT16().");
562+
}
563+
564+
void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(
565+
const MCInst &MI, unsigned OpNo, APInt &Op,
566+
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
567+
const MCOperand &MO = MI.getOperand(OpNo);
568+
if (MO.isReg()) {
569+
uint16_t Encoding = MRI.getEncodingValue(MO.getReg());
570+
unsigned RegIdx = Encoding & AMDGPU::EncValues::REG_IDX_MASK;
571+
bool IsHi = Encoding & AMDGPU::EncValues::IS_HI;
572+
bool IsVGPR = Encoding & AMDGPU::EncValues::IS_VGPR;
573+
assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!");
574+
Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx;
575+
return;
576+
}
577+
getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
578+
}
579+
550580
void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
551581
const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
552582
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -314,6 +314,7 @@ namespace AMDGPU {
314314
namespace EncValues { // Encoding values of enum9/8/7 operands
315315

316316
enum : unsigned {
317+
REG_IDX_MASK = 255,
317318
SGPR_MIN = 0,
318319
SGPR_MAX_SI = 101,
319320
SGPR_MAX_GFX10 = 105,
@@ -329,7 +330,8 @@ enum : unsigned {
329330
LITERAL_CONST = 255,
330331
VGPR_MIN = 256,
331332
VGPR_MAX = 511,
332-
IS_VGPR = 256 // Indicates VGPR or AGPR
333+
IS_VGPR = 256, // Indicates VGPR or AGPR
334+
IS_HI = 512, // High 16-bit register.
333335
};
334336

335337
} // namespace EncValues

‎llvm/lib/Target/AMDGPU/SIInstrFormats.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -304,6 +304,16 @@ def CPolBit {
304304

305305
class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
306306

307+
def VOPDstOperand_t16 : VOPDstOperand <VGPR_16> {
308+
let EncoderMethod = "getMachineOpValueT16";
309+
let DecoderMethod = "DecodeVGPR_16RegisterClass";
310+
}
311+
312+
def VOPDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> {
313+
let EncoderMethod = "getMachineOpValueT16Lo128";
314+
let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";
315+
}
316+
307317
class VINTRPe <bits<2> op> : Enc32 {
308318
bits<8> vdst;
309319
bits<8> vsrc;

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