Implement Correct Matching Logic

Author: Sh0g0-1758

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -2841,16 +2841,17 @@ static SDValue combineFixedwidthToAVG(SDNode *N, SelectionDAG &DAG) {
   ConstantSDNode *N1C = isConstOrConstSplat(Lshr.getOperand(1));
   if (!N1C || N1C->getAPIntValue() != 1)
     return SDValue();
-  EVT VT = And.getValueType();
+  EVT VT = And1.getValueType();
+  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
   if (VT.isVector())
-    return SDValue();
+    VT = EVT::getVectorVT(*DAG.getContext(), NVT, VT.getVectorElementCount());
+  else
+    VT = NVT;
   SDLoc DL(N);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   if (!TLI.isOperationLegalOrCustom(ISD::AVGFLOORU, VT))
     return SDValue();
-  return DAG.getNode(ISD::AVGFLOORU, DL, VT,
-                     DAG.getExtOrTrunc(false, And1, DL, VT),
-                     DAG.getExtOrTrunc(false, And2, DL, VT));
+  return DAG.getNode(ISD::AVGFLOORU, DL, VT, And1, And2);
 }
 
 SDValue DAGCombiner::visitADD(SDNode *N) {

llvm/test/CodeGen/AArch64/hadd-combine.ll

@@ -859,8 +859,23 @@ define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-define <4 x i32> @fixedwidth(<4 x i32> %a0, <4 x i32> %a1)  {
-; CHECK-LABEL: fixedwidth:
+define i4 @uhadd_fixedwidth_i4(i4 %a0, i4 %a1)  {
+; CHECK-LABEL: uhadd_fixedwidth_i4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    eor w8, w0, w1
+; CHECK-NEXT:    and w9, w0, w1
+; CHECK-NEXT:    and w8, w8, #0xe
+; CHECK-NEXT:    add w0, w9, w8, lsr #1
+; CHECK-NEXT:    ret
+  %and = and i4 %a0, %a1
+  %xor = xor i4 %a0, %a1
+  %srl = lshr i4 %xor, 1
+  %res = add i4 %and, %srl
+  ret i4 %res
+}
+
+define <4 x i32> @uhadd_fixedwidth_v4i32(<4 x i32> %a0, <4 x i32> %a1)  {
+; CHECK-LABEL: uhadd_fixedwidth_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and v2.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    eor v0.16b, v0.16b, v1.16b