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[RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions
Marking them as `hasSideEffects=1` stops some optimizations. According to `Target.td`: > // Does the instruction have side effects that are not captured by any > // operands of the instruction or other flags? > bit hasSideEffects = ?; It seems we don't need to set `hasSideEffects` for vleNff since we have modelled `vl` as an output operand. As for saturating instructions, I think that explicit Def/Use list is kind of side effects captured by any operands of the instruction, so we don't need to set `hasSideEffects` either. And I have just investigated AArch64's implementation, they don't set this flag and don't add `Def` list. These changes make optimizations like `performCombineVMergeAndVOps` and MachineCSE possible for these instructions. As a consequence, `copyprop.mir` can't test what we want to test in https://reviews.llvm.org/D155140, so we replace `vssra.vi` with a VCIX instruction (it has side effects). Reviewers: jacquesguan, topperc, preames, asb, lukel97 Reviewed By: topperc, lukel97 Pull Request: #90049
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‎llvm/include/llvm/IR/IntrinsicsRISCV.td

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -661,7 +661,7 @@ let TargetPrefix = "riscv" in {
661661
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
662662
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
663663
llvm_anyint_ty],
664-
[IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
664+
[IntrNoMem]>, RISCVVIntrinsic {
665665
let ScalarOperand = 2;
666666
let VLOperand = 3;
667667
}
@@ -684,7 +684,7 @@ let TargetPrefix = "riscv" in {
684684
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
685685
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
686686
LLVMMatchType<2>],
687-
[ImmArg<ArgIndex<5>>, IntrNoMem, IntrHasSideEffects]>, RISCVVIntrinsic {
687+
[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
688688
let ScalarOperand = 2;
689689
let VLOperand = 4;
690690
}
@@ -708,7 +708,7 @@ let TargetPrefix = "riscv" in {
708708
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
709709
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
710710
llvm_anyint_ty, LLVMMatchType<2>],
711-
[ImmArg<ArgIndex<3>>, IntrNoMem, IntrHasSideEffects]>,
711+
[ImmArg<ArgIndex<3>>, IntrNoMem]>,
712712
RISCVVIntrinsic {
713713
let VLOperand = 4;
714714
}
@@ -721,7 +721,7 @@ let TargetPrefix = "riscv" in {
721721
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_any_ty,
722722
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
723723
LLVMMatchType<2>, LLVMMatchType<2>],
724-
[ImmArg<ArgIndex<4>>,ImmArg<ArgIndex<6>>, IntrNoMem, IntrHasSideEffects]>,
724+
[ImmArg<ArgIndex<4>>,ImmArg<ArgIndex<6>>, IntrNoMem]>,
725725
RISCVVIntrinsic {
726726
let VLOperand = 5;
727727
}
@@ -733,7 +733,7 @@ let TargetPrefix = "riscv" in {
733733
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
734734
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
735735
llvm_anyint_ty, LLVMMatchType<3>],
736-
[ImmArg<ArgIndex<3>>, IntrNoMem, IntrHasSideEffects]>,
736+
[ImmArg<ArgIndex<3>>, IntrNoMem]>,
737737
RISCVVIntrinsic {
738738
let VLOperand = 4;
739739
}
@@ -746,8 +746,7 @@ let TargetPrefix = "riscv" in {
746746
[LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
747747
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
748748
LLVMMatchType<3>, LLVMMatchType<3>],
749-
[ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem,
750-
IntrHasSideEffects]>, RISCVVIntrinsic {
749+
[ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem]>, RISCVVIntrinsic {
751750
let VLOperand = 5;
752751
}
753752
// Input: (vector_in, vector_in, scalar_in, vl, policy)

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3668,7 +3668,6 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
36683668
}
36693669

36703670
// Skip if True has side effect.
3671-
// TODO: Support vleff and vlsegff.
36723671
if (TII->get(TrueOpc).hasUnmodeledSideEffects())
36733672
return false;
36743673

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6232,7 +6232,7 @@ defm PseudoVSUX : VPseudoIStore<Ordered=false>;
62326232
//===----------------------------------------------------------------------===//
62336233

62346234
// vleff may update VL register
6235-
let hasSideEffects = 1, Defs = [VL] in
6235+
let Defs = [VL] in
62366236
defm PseudoVL : VPseudoFFLoad;
62376237

62386238
//===----------------------------------------------------------------------===//
@@ -6248,7 +6248,7 @@ defm PseudoVSOXSEG : VPseudoISegStore<Ordered=true>;
62486248
defm PseudoVSUXSEG : VPseudoISegStore<Ordered=false>;
62496249

62506250
// vlseg<nf>e<eew>ff.v may update VL register
6251-
let hasSideEffects = 1, Defs = [VL] in {
6251+
let Defs = [VL] in {
62526252
defm PseudoVLSEG : VPseudoUSSegLoadFF;
62536253
}
62546254

@@ -6450,7 +6450,7 @@ defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I;
64506450
//===----------------------------------------------------------------------===//
64516451
// 12.1. Vector Single-Width Saturating Add and Subtract
64526452
//===----------------------------------------------------------------------===//
6453-
let Defs = [VXSAT], hasSideEffects = 1 in {
6453+
let Defs = [VXSAT] in {
64546454
defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI<Commutable=1>;
64556455
defm PseudoVSADD : VPseudoVSALU_VV_VX_VI<Commutable=1>;
64566456
defm PseudoVSSUBU : VPseudoVSALU_VV_VX;
@@ -6468,7 +6468,7 @@ defm PseudoVASUB : VPseudoVAALU_VV_VX_RM;
64686468
//===----------------------------------------------------------------------===//
64696469
// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
64706470
//===----------------------------------------------------------------------===//
6471-
let Defs = [VXSAT], hasSideEffects = 1 in {
6471+
let Defs = [VXSAT] in {
64726472
defm PseudoVSMUL : VPseudoVSMUL_VV_VX_RM;
64736473
}
64746474

@@ -6481,7 +6481,7 @@ defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM<uimm5>;
64816481
//===----------------------------------------------------------------------===//
64826482
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
64836483
//===----------------------------------------------------------------------===//
6484-
let Defs = [VXSAT], hasSideEffects = 1 in {
6484+
let Defs = [VXSAT] in {
64856485
defm PseudoVNCLIP : VPseudoVNCLP_WV_WX_WI_RM;
64866486
defm PseudoVNCLIPU : VPseudoVNCLP_WV_WX_WI_RM;
64876487
}

‎llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Lines changed: 27 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,10 @@ define void @last_chance_recoloring_failure() {
2626
; CHECK-NEXT: li a0, 55
2727
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
2828
; CHECK-NEXT: vloxseg2ei32.v v16, (a0), v8
29-
; CHECK-NEXT: addi a0, sp, 16
29+
; CHECK-NEXT: csrr a0, vlenb
30+
; CHECK-NEXT: slli a0, a0, 3
31+
; CHECK-NEXT: add a0, sp, a0
32+
; CHECK-NEXT: addi a0, a0, 16
3033
; CHECK-NEXT: csrr a1, vlenb
3134
; CHECK-NEXT: slli a1, a1, 2
3235
; CHECK-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
@@ -37,37 +40,24 @@ define void @last_chance_recoloring_failure() {
3740
; CHECK-NEXT: li s0, 36
3841
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
3942
; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t
40-
; CHECK-NEXT: csrr a0, vlenb
41-
; CHECK-NEXT: slli a0, a0, 3
42-
; CHECK-NEXT: add a0, sp, a0
43-
; CHECK-NEXT: addi a0, a0, 16
43+
; CHECK-NEXT: addi a0, sp, 16
4444
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
4545
; CHECK-NEXT: call func
46-
; CHECK-NEXT: li a0, 32
47-
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
48-
; CHECK-NEXT: vrgather.vv v16, v8, v12, v0.t
4946
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
50-
; CHECK-NEXT: addi a1, sp, 16
51-
; CHECK-NEXT: csrr a2, vlenb
52-
; CHECK-NEXT: slli a2, a2, 2
53-
; CHECK-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
54-
; CHECK-NEXT: add a1, a1, a2
55-
; CHECK-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
56-
; CHECK-NEXT: csrr a1, vlenb
57-
; CHECK-NEXT: slli a1, a1, 3
58-
; CHECK-NEXT: add a1, sp, a1
59-
; CHECK-NEXT: addi a1, a1, 16
60-
; CHECK-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
61-
; CHECK-NEXT: vfwsub.wv v8, v0, v20
62-
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
63-
; CHECK-NEXT: vssubu.vv v16, v16, v8, v0.t
64-
; CHECK-NEXT: vsetvli zero, s0, e32, m8, tu, mu
6547
; CHECK-NEXT: csrr a0, vlenb
6648
; CHECK-NEXT: slli a0, a0, 3
6749
; CHECK-NEXT: add a0, sp, a0
6850
; CHECK-NEXT: addi a0, a0, 16
69-
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
70-
; CHECK-NEXT: vfdiv.vv v8, v16, v8, v0.t
51+
; CHECK-NEXT: csrr a1, vlenb
52+
; CHECK-NEXT: slli a1, a1, 2
53+
; CHECK-NEXT: vl4r.v v16, (a0) # Unknown-size Folded Reload
54+
; CHECK-NEXT: add a0, a0, a1
55+
; CHECK-NEXT: vl4r.v v20, (a0) # Unknown-size Folded Reload
56+
; CHECK-NEXT: addi a0, sp, 16
57+
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
58+
; CHECK-NEXT: vfwsub.wv v8, v24, v16
59+
; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, mu
60+
; CHECK-NEXT: vfdiv.vv v8, v24, v8, v0.t
7161
; CHECK-NEXT: vse32.v v8, (a0)
7262
; CHECK-NEXT: csrr a0, vlenb
7363
; CHECK-NEXT: slli a0, a0, 4
@@ -109,25 +99,20 @@ define void @last_chance_recoloring_failure() {
10999
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
110100
; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
111101
; SUBREGLIVENESS-NEXT: call func
112-
; SUBREGLIVENESS-NEXT: li a0, 32
113-
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
114-
; SUBREGLIVENESS-NEXT: vrgather.vv v16, v8, v12, v0.t
115102
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
103+
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
104+
; SUBREGLIVENESS-NEXT: slli a0, a0, 3
105+
; SUBREGLIVENESS-NEXT: add a0, sp, a0
106+
; SUBREGLIVENESS-NEXT: addi a0, a0, 16
116107
; SUBREGLIVENESS-NEXT: csrr a1, vlenb
117-
; SUBREGLIVENESS-NEXT: slli a1, a1, 3
118-
; SUBREGLIVENESS-NEXT: add a1, sp, a1
119-
; SUBREGLIVENESS-NEXT: addi a1, a1, 16
120-
; SUBREGLIVENESS-NEXT: csrr a2, vlenb
121-
; SUBREGLIVENESS-NEXT: slli a2, a2, 2
122-
; SUBREGLIVENESS-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
123-
; SUBREGLIVENESS-NEXT: add a1, a1, a2
124-
; SUBREGLIVENESS-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
125-
; SUBREGLIVENESS-NEXT: addi a1, sp, 16
126-
; SUBREGLIVENESS-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
127-
; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v20
128-
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, tu, mu
129-
; SUBREGLIVENESS-NEXT: vssubu.vv v16, v16, v8, v0.t
130-
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e32, m8, tu, mu
108+
; SUBREGLIVENESS-NEXT: slli a1, a1, 2
109+
; SUBREGLIVENESS-NEXT: vl4r.v v16, (a0) # Unknown-size Folded Reload
110+
; SUBREGLIVENESS-NEXT: add a0, a0, a1
111+
; SUBREGLIVENESS-NEXT: vl4r.v v20, (a0) # Unknown-size Folded Reload
112+
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
113+
; SUBREGLIVENESS-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
114+
; SUBREGLIVENESS-NEXT: vfwsub.wv v8, v24, v16
115+
; SUBREGLIVENESS-NEXT: vsetvli zero, zero, e32, m8, tu, mu
131116
; SUBREGLIVENESS-NEXT: vfdiv.vv v8, v24, v8, v0.t
132117
; SUBREGLIVENESS-NEXT: vse32.v v8, (a0)
133118
; SUBREGLIVENESS-NEXT: csrr a0, vlenb

‎llvm/test/CodeGen/RISCV/rvv/commutable.ll

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -655,10 +655,9 @@ define <vscale x 1 x i64> @commutable_vsadd_vv(<vscale x 1 x i64> %0, <vscale x
655655
; CHECK-LABEL: commutable_vsadd_vv:
656656
; CHECK: # %bb.0: # %entry
657657
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
658-
; CHECK-NEXT: vsadd.vv v10, v8, v9
659-
; CHECK-NEXT: vsadd.vv v8, v9, v8
658+
; CHECK-NEXT: vsadd.vv v8, v8, v9
660659
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
661-
; CHECK-NEXT: vadd.vv v8, v10, v8
660+
; CHECK-NEXT: vadd.vv v8, v8, v8
662661
; CHECK-NEXT: ret
663662
entry:
664663
%a = call <vscale x 1 x i64> @llvm.riscv.vsadd.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2)
@@ -673,7 +672,7 @@ define <vscale x 1 x i64> @commutable_vsadd_vv_masked(<vscale x 1 x i64> %0, <vs
673672
; CHECK: # %bb.0:
674673
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
675674
; CHECK-NEXT: vsadd.vv v10, v8, v9, v0.t
676-
; CHECK-NEXT: vsadd.vv v8, v9, v8, v0.t
675+
; CHECK-NEXT: vsadd.vv v8, v8, v9, v0.t
677676
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
678677
; CHECK-NEXT: vadd.vv v8, v10, v8
679678
; CHECK-NEXT: ret
@@ -689,10 +688,9 @@ define <vscale x 1 x i64> @commutable_vsaddu_vv(<vscale x 1 x i64> %0, <vscale x
689688
; CHECK-LABEL: commutable_vsaddu_vv:
690689
; CHECK: # %bb.0: # %entry
691690
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
692-
; CHECK-NEXT: vsaddu.vv v10, v8, v9
693-
; CHECK-NEXT: vsaddu.vv v8, v9, v8
691+
; CHECK-NEXT: vsaddu.vv v8, v8, v9
694692
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
695-
; CHECK-NEXT: vadd.vv v8, v10, v8
693+
; CHECK-NEXT: vadd.vv v8, v8, v8
696694
; CHECK-NEXT: ret
697695
entry:
698696
%a = call <vscale x 1 x i64> @llvm.riscv.vsaddu.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2)
@@ -707,7 +705,7 @@ define <vscale x 1 x i64> @commutable_vsaddu_vv_masked(<vscale x 1 x i64> %0, <v
707705
; CHECK: # %bb.0:
708706
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
709707
; CHECK-NEXT: vsaddu.vv v10, v8, v9, v0.t
710-
; CHECK-NEXT: vsaddu.vv v8, v9, v8, v0.t
708+
; CHECK-NEXT: vsaddu.vv v8, v8, v9, v0.t
711709
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
712710
; CHECK-NEXT: vadd.vv v8, v10, v8
713711
; CHECK-NEXT: ret
@@ -794,10 +792,9 @@ define <vscale x 1 x i64> @commutable_vsmul_vv(<vscale x 1 x i64> %0, <vscale x
794792
; CHECK: # %bb.0: # %entry
795793
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
796794
; CHECK-NEXT: csrwi vxrm, 0
797-
; CHECK-NEXT: vsmul.vv v10, v8, v9
798-
; CHECK-NEXT: vsmul.vv v8, v9, v8
795+
; CHECK-NEXT: vsmul.vv v8, v8, v9
799796
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
800-
; CHECK-NEXT: vadd.vv v8, v10, v8
797+
; CHECK-NEXT: vadd.vv v8, v8, v8
801798
; CHECK-NEXT: ret
802799
entry:
803800
%a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen 0, iXLen %2)
@@ -813,7 +810,7 @@ define <vscale x 1 x i64> @commutable_vsmul_vv_masked(<vscale x 1 x i64> %0, <vs
813810
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
814811
; CHECK-NEXT: csrwi vxrm, 0
815812
; CHECK-NEXT: vsmul.vv v10, v8, v9, v0.t
816-
; CHECK-NEXT: vsmul.vv v8, v9, v8, v0.t
813+
; CHECK-NEXT: vsmul.vv v8, v8, v9, v0.t
817814
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
818815
; CHECK-NEXT: vadd.vv v8, v10, v8
819816
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/copyprop.mir

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,28 @@
11
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2-
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -start-after=finalize-isel | FileCheck %s
2+
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v,+xsfvcp -start-after=finalize-isel | FileCheck %s
33

44
--- |
55
define void @foo() {
66
; CHECK-LABEL: foo:
77
; CHECK: # %bb.0: # %entry
88
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
99
; CHECK-NEXT: vmsne.vi v0, v8, 0
10-
; CHECK-NEXT: vsll.vi v9, v8, 5
11-
; CHECK-NEXT: vmerge.vim v9, v9, -1, v0
12-
; CHECK-NEXT: csrwi vxrm, 0
13-
; CHECK-NEXT: vssra.vi v8, v8, 2
10+
; CHECK-NEXT: vsll.vi v8, v8, 5
11+
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
12+
; CHECK-NEXT: sf.vc.v.x 3, 31, v9, a1
1413
; CHECK-NEXT: bgeu a0, zero, .LBB0_3
1514
; CHECK-NEXT: # %bb.1: # %entry
1615
; CHECK-NEXT: li a2, 128
1716
; CHECK-NEXT: bltu a0, a2, .LBB0_4
1817
; CHECK-NEXT: .LBB0_2: # %entry
19-
; CHECK-NEXT: vse64.v v8, (a1)
18+
; CHECK-NEXT: vse64.v v9, (a1)
2019
; CHECK-NEXT: ret
2120
; CHECK-NEXT: .LBB0_3:
22-
; CHECK-NEXT: vmv.v.i v8, 0
21+
; CHECK-NEXT: vmv.v.i v9, 0
2322
; CHECK-NEXT: li a2, 128
2423
; CHECK-NEXT: bgeu a0, a2, .LBB0_2
2524
; CHECK-NEXT: .LBB0_4: # %entry
26-
; CHECK-NEXT: vse64.v v9, (a1)
25+
; CHECK-NEXT: vse64.v v8, (a1)
2726
; CHECK-NEXT: ret
2827
entry:
2928
ret void
@@ -51,7 +50,7 @@ body: |
5150
%26:vrnov0 = IMPLICIT_DEF
5251
%25:vrnov0 = PseudoVMERGE_VIM_M1 %26, %17, -1, $v0, 1, 6 /* e64 */
5352
%pt8:vr = IMPLICIT_DEF
54-
%29:vr = PseudoVSSRA_VI_M1 %pt8, %3, 2, 0, 1, 6 /* e64 */, 0
53+
%29:vr = PseudoVC_V_X_SE_M1 3, 31, %2, 1, 6 /* e64 */, implicit-def dead $vcix_state, implicit $vcix_state
5554
%pt9:vr = IMPLICIT_DEF
5655
%30:vr = PseudoVMV_V_I_M1 %pt9, 0, 1, 6 /* e64 */, 0
5756
BGEU %1, $x0, %bb.2

‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store(<vscale x 2 x i32> %passthru, ptr %p, <vscale
194194
ret void
195195
}
196196

197-
; FIXME: Merge vmerge.vvm and vleffN.v
198197
declare { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32(<vscale x 2 x i32>, ptr, i64)
199198
define <vscale x 2 x i32> @vpmerge_vleff(<vscale x 2 x i32> %passthru, ptr %p, <vscale x 2 x i1> %m, i32 zeroext %vl) {
200199
; CHECK-LABEL: vpmerge_vleff:
201200
; CHECK: # %bb.0:
202-
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
203-
; CHECK-NEXT: vle32ff.v v9, (a0)
204-
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
205-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
201+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu
202+
; CHECK-NEXT: vle32ff.v v8, (a0), v0.t
206203
; CHECK-NEXT: ret
207204
%1 = zext i32 %vl to i64
208205
%a = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32(<vscale x 2 x i32> undef, ptr %p, i64 %1)
@@ -634,14 +631,11 @@ define void @vpselect_vpload_store(<vscale x 2 x i32> %passthru, ptr %p, <vscale
634631
ret void
635632
}
636633

637-
; FIXME: select vselect.vvm and vleffN.v
638634
define <vscale x 2 x i32> @vpselect_vleff(<vscale x 2 x i32> %passthru, ptr %p, <vscale x 2 x i1> %m, i32 zeroext %vl) {
639635
; CHECK-LABEL: vpselect_vleff:
640636
; CHECK: # %bb.0:
641-
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
642-
; CHECK-NEXT: vle32ff.v v9, (a0)
643-
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
644-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
637+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
638+
; CHECK-NEXT: vle32ff.v v8, (a0), v0.t
645639
; CHECK-NEXT: ret
646640
%1 = zext i32 %vl to i64
647641
%a = call { <vscale x 2 x i32>, i64 } @llvm.riscv.vleff.nxv2i32(<vscale x 2 x i32> undef, ptr %p, i64 %1)
@@ -898,22 +892,20 @@ define <vscale x 2 x i32> @vpselect_trunc(<vscale x 2 x i32> %passthru, <vscale
898892
define void @test_dag_loop() {
899893
; CHECK-LABEL: test_dag_loop:
900894
; CHECK: # %bb.0: # %entry
901-
; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma
902-
; CHECK-NEXT: vle16.v v8, (zero)
903895
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
904896
; CHECK-NEXT: vmclr.m v0
905-
; CHECK-NEXT: vmv.v.i v16, 0
897+
; CHECK-NEXT: vmv.v.i v8, 0
906898
; CHECK-NEXT: vsetivli zero, 0, e8, m4, tu, mu
907-
; CHECK-NEXT: vmv4r.v v20, v16
908-
; CHECK-NEXT: vssubu.vx v20, v16, zero, v0.t
899+
; CHECK-NEXT: vmv4r.v v12, v8
900+
; CHECK-NEXT: vssubu.vx v12, v8, zero, v0.t
909901
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
910-
; CHECK-NEXT: vmseq.vv v0, v20, v16
902+
; CHECK-NEXT: vmseq.vv v0, v12, v8
911903
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
912-
; CHECK-NEXT: vmv.v.i v16, 0
913-
; CHECK-NEXT: vsetivli zero, 1, e16, m8, tu, ma
914-
; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
904+
; CHECK-NEXT: vmv.v.i v8, 0
905+
; CHECK-NEXT: vsetivli zero, 1, e16, m8, tu, mu
906+
; CHECK-NEXT: vle16.v v8, (zero), v0.t
915907
; CHECK-NEXT: vsetivli zero, 0, e16, m8, ta, ma
916-
; CHECK-NEXT: vse16.v v16, (zero)
908+
; CHECK-NEXT: vse16.v v8, (zero)
917909
; CHECK-NEXT: ret
918910
entry:
919911
%0 = call <vscale x 32 x i16> @llvm.riscv.vle.nxv32i16.i64(<vscale x 32 x i16> undef, ptr null, i64 1)

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