@@ -14,13 +14,13 @@ body: |
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
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; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 1, implicit $eflags
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- ; CHECK-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def $eflags
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+ ; CHECK-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
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; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
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; CHECK-NEXT: CCMP32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
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; CHECK-NEXT: RET 0, $al
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MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
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%1:gr64 = COPY $eflags
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- %2:gr32 = ADD32rr $edi, $edi, implicit-def $eflags
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+ %2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
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$eflags = COPY %1
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CCMP32rr %2, %2, 0, 1, implicit-def $eflags, implicit $eflags
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RET 0, $al
@@ -37,13 +37,13 @@ body: |
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
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; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 1, implicit $eflags
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- ; CHECK-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def $eflags
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+ ; CHECK-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
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; CHECK-NEXT: TEST8rr [[SETCCr]], [[SETCCr]], implicit-def $eflags
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; CHECK-NEXT: CTEST32rr [[ADD32rr]], [[ADD32rr]], 0, 5, implicit-def $eflags, implicit killed $eflags
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; CHECK-NEXT: RET 0, $al
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MUL32r $edi, implicit-def $eax, implicit-def dead $edx, implicit-def $eflags, implicit $eax
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%1:gr64 = COPY $eflags
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- %2:gr32 = ADD32rr $edi, $edi, implicit-def $eflags
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+ %2:gr32 = ADD32rr $edi, $edi, implicit-def dead $eflags
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$eflags = COPY %1
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CTEST32rr %2, %2, 0, 1, implicit-def $eflags, implicit $eflags
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RET 0, $al
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