[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV

Author: LiqinWeng

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -1507,6 +1507,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   // Disable strict node mutation.
   IsStrictFPEnabled = true;
+  EnableExtLdPromotion = true;
 
   // Let the subtarget decide if a predictable select is more expensive than the
   // corresponding branch. This information is used in CGP/SelectOpt to decide

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

@@ -1989,3 +1989,35 @@ bool RISCVTTIImpl::areInlineCompatible(const Function *Caller,
   // target-features.
   return (CallerBits & CalleeBits) == CalleeBits;
 }
+
+/// See if \p I should be considered for address type promotion. We check if \p
+/// I is a sext with right type and used in memory accesses. If it used in a
+/// "complex" getelementptr, we allow it to be promoted without finding other
+/// sext instructions that sign extended the same initial value. A getelementptr
+/// is considered as "complex" if it has more than 2 operands.
+bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
+    const Instruction &I, bool &AllowPromotionWithoutCommonHeader) {
+  bool Considerable = false;
+  AllowPromotionWithoutCommonHeader = false;
+  if (!isa<SExtInst>(&I))
+    return false;
+  Type *ConsideredSExtType =
+      Type::getInt64Ty(I.getParent()->getParent()->getContext());
+  if (I.getType() != ConsideredSExtType)
+    return false;
+  // See if the sext is the one with the right type and used in at least one
+  // GetElementPtrInst.
+  for (const User *U : I.users()) {
+    if (const GetElementPtrInst *GEPInst = dyn_cast<GetElementPtrInst>(U)) {
+      Considerable = true;
+      // A getelementptr is considered as "complex" if it has more than 2
+      // operands. We will promote a SExt used in such complex GEP as we
+      // expect some computation to be merged if they are done on 64 bits.
+      if (GEPInst->getNumOperands() > 2) {
+        AllowPromotionWithoutCommonHeader = true;
+        break;
+      }
+    }
+  }
+  return Considerable;
+}

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

@@ -397,7 +397,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
   bool shouldFoldTerminatingConditionAfterLSR() const {
     return true;
   }
-
+  bool
+  shouldConsiderAddressTypePromotion(const Instruction &I,
+                                     bool &AllowPromotionWithoutCommonHeader);
   std::optional<unsigned> getMinPageSize() const { return 4096; }
 };
 

llvm/test/CodeGen/RISCV/riscv-codegen-prepare-atp.ll

@@ -11,11 +11,11 @@ define void @promoteTwoOne(i32 %i, i32 %j, ptr %P1, ptr %P2 ) {
 ; CHECK-LABEL: define void @promoteTwoOne(
 ; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[I]], [[J]]
-; CHECK-NEXT:    [[S:%.*]] = sext i32 [[ADD]] to i64
+; CHECK-NEXT:    [[S2:%.*]] = sext i32 [[I]] to i64
+; CHECK-NEXT:    [[PROMOTED2:%.*]] = sext i32 [[J]] to i64
+; CHECK-NEXT:    [[S:%.*]] = add nsw i64 [[S2]], [[PROMOTED2]]
 ; CHECK-NEXT:    [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
 ; CHECK-NEXT:    store i64 [[S]], ptr [[ADDR1]], align 8
-; CHECK-NEXT:    [[S2:%.*]] = sext i32 [[I]] to i64
 ; CHECK-NEXT:    [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
 ; CHECK-NEXT:    store i64 [[S2]], ptr [[ADDR2]], align 8
 ; CHECK-NEXT:    ret void
@@ -36,12 +36,13 @@ define void @promoteTwoTwo(i32 %i, i32 %j, i32 %k, ptr %P1, ptr %P2) {
 ; CHECK-LABEL: define void @promoteTwoTwo(
 ; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], i32 [[K:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[ADD1:%.*]] = add nsw i32 [[J]], [[I]]
-; CHECK-NEXT:    [[S:%.*]] = sext i32 [[ADD1]] to i64
+; CHECK-NEXT:    [[PROMOTED3:%.*]] = sext i32 [[J]] to i64
+; CHECK-NEXT:    [[PROMOTED4:%.*]] = sext i32 [[I]] to i64
+; CHECK-NEXT:    [[S:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED4]]
 ; CHECK-NEXT:    [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
 ; CHECK-NEXT:    store i64 [[S]], ptr [[ADDR1]], align 8
-; CHECK-NEXT:    [[ADD2:%.*]] = add nsw i32 [[J]], [[K]]
-; CHECK-NEXT:    [[S2:%.*]] = sext i32 [[ADD2]] to i64
+; CHECK-NEXT:    [[PROMOTED2:%.*]] = sext i32 [[K]] to i64
+; CHECK-NEXT:    [[S2:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED2]]
 ; CHECK-NEXT:    [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
 ; CHECK-NEXT:    store i64 [[S2]], ptr [[ADDR2]], align 8
 ; CHECK-NEXT:    ret void
@@ -62,11 +63,10 @@ define i64 @promoteGEPSunk(i1 %cond, ptr %base, i32 %i) {
 ; CHECK-LABEL: define i64 @promoteGEPSunk(
 ; CHECK-SAME: i1 [[COND:%.*]], ptr [[BASE:%.*]], i32 [[I:%.*]]) {
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[I]], 1
-; CHECK-NEXT:    [[S:%.*]] = sext i32 [[ADD]] to i64
+; CHECK-NEXT:    [[PROMOTED1:%.*]] = sext i32 [[I]] to i64
+; CHECK-NEXT:    [[S:%.*]] = add nsw i64 [[PROMOTED1]], 1
 ; CHECK-NEXT:    [[ADDR:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S]]
-; CHECK-NEXT:    [[ADD2:%.*]] = add nsw i32 [[I]], 2
-; CHECK-NEXT:    [[S2:%.*]] = sext i32 [[ADD2]] to i64
+; CHECK-NEXT:    [[S2:%.*]] = add nsw i64 [[PROMOTED1]], 2
 ; CHECK-NEXT:    [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S2]]
 ; CHECK-NEXT:    br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_THEN2:%.*]]
 ; CHECK:       if.then: