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[LowerTypeTests] Regenerate test checks (NFC)
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‎llvm/test/Transforms/LowerTypeTests/import.ll

Lines changed: 201 additions & 119 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
12
; RUN: opt -mtriple=x86_64-unknown-linux -S -passes=lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import.yaml %s | FileCheck --check-prefixes=CHECK,X86 %s
23
; RUN: opt -mtriple=aarch64-unknown-linux -S -passes=lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import.yaml %s | FileCheck --check-prefixes=CHECK,ARM %s
34

@@ -31,156 +32,237 @@ declare i1 @llvm.type.test(ptr %ptr, metadata %bitset) nounwind readnone
3132
; X86-DAG: @__typeid_allones7_align = external hidden global [0 x i8], !absolute_symbol !0
3233
; X86-DAG: @__typeid_allones7_size_m1 = external hidden global [0 x i8], !absolute_symbol !5
3334

34-
; CHECK: define i1 @allones7(ptr [[p:%.*]])
3535
define i1 @allones7(ptr %p) {
36-
; CHECK-NEXT: [[pi:%.*]] = ptrtoint ptr [[p]] to i64
37-
; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
38-
; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64)
39-
; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64)
40-
; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 1
41-
; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 63
42-
; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
43-
; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
44-
; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 42
45-
; CHECK-NEXT: ret i1 [[ule]]
36+
; X86-LABEL: define i1 @allones7(
37+
; X86-SAME: ptr [[P:%.*]]) {
38+
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
39+
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
40+
; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_allones7_align to i8) to i64)
41+
; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones7_align to i8)) to i64)
42+
; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
43+
; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
44+
; X86-NEXT: ret i1 [[TMP6]]
45+
;
46+
; ARM-LABEL: define i1 @allones7(
47+
; ARM-SAME: ptr [[P:%.*]]) {
48+
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
49+
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones7_global_addr to i64)
50+
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 1
51+
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 63
52+
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
53+
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 42
54+
; ARM-NEXT: ret i1 [[TMP6]]
55+
;
4656
%x = call i1 @llvm.type.test(ptr %p, metadata !"allones7")
4757
ret i1 %x
4858
}
4959

50-
; CHECK: define i1 @allones32(ptr [[p:%.*]])
5160
define i1 @allones32(ptr %p) {
52-
; CHECK-NEXT: [[pi:%.*]] = ptrtoint ptr [[p]] to i64
53-
; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
54-
; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (ptr @__typeid_allones32_align to i8) to i64)
55-
; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones32_align to i8)) to i64)
56-
; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 2
57-
; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 62
58-
; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
59-
; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
60-
; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 12345
61-
; CHECK-NEXT: ret i1 [[ule]]
61+
; X86-LABEL: define i1 @allones32(
62+
; X86-SAME: ptr [[P:%.*]]) {
63+
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
64+
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
65+
; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_allones32_align to i8) to i64)
66+
; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_allones32_align to i8)) to i64)
67+
; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
68+
; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
69+
; X86-NEXT: ret i1 [[TMP6]]
70+
;
71+
; ARM-LABEL: define i1 @allones32(
72+
; ARM-SAME: ptr [[P:%.*]]) {
73+
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
74+
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_allones32_global_addr to i64)
75+
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 2
76+
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 62
77+
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
78+
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 12345
79+
; ARM-NEXT: ret i1 [[TMP6]]
80+
;
6281
%x = call i1 @llvm.type.test(ptr %p, metadata !"allones32")
6382
ret i1 %x
6483
}
6584

66-
; CHECK: define i1 @bytearray7(ptr [[p:%.*]])
6785
define i1 @bytearray7(ptr %p) {
68-
; CHECK-NEXT: [[pi:%.*]] = ptrtoint ptr [[p]] to i64
69-
; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
70-
; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64)
71-
; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64)
72-
; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 3
73-
; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 61
74-
; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
75-
; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
76-
; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 43
77-
; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
78-
79-
; CHECK: [[t]]:
80-
; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[or]]
81-
; CHECK-NEXT: [[load:%.*]] = load i8, ptr [[gep]]
82-
; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
83-
; ARM-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (ptr inttoptr (i64 64 to ptr) to i8)
84-
; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0
85-
; CHECK-NEXT: br label %[[f]]
86-
87-
; CHECK: [[f]]:
88-
; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
89-
; CHECK-NEXT: ret i1 [[phi]]
86+
; X86-LABEL: define i1 @bytearray7(
87+
; X86-SAME: ptr [[P:%.*]]) {
88+
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
89+
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
90+
; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_bytearray7_align to i8) to i64)
91+
; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray7_align to i8)) to i64)
92+
; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
93+
; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
94+
; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
95+
; X86: 7:
96+
; X86-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP5]]
97+
; X86-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
98+
; X86-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
99+
; X86-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
100+
; X86-NEXT: br label [[TMP12]]
101+
; X86: 12:
102+
; X86-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
103+
; X86-NEXT: ret i1 [[TMP13]]
104+
;
105+
; ARM-LABEL: define i1 @bytearray7(
106+
; ARM-SAME: ptr [[P:%.*]]) {
107+
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
108+
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray7_global_addr to i64)
109+
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
110+
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 61
111+
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
112+
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 43
113+
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
114+
; ARM: 7:
115+
; ARM-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP5]]
116+
; ARM-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
117+
; ARM-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr inttoptr (i64 64 to ptr) to i8)
118+
; ARM-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
119+
; ARM-NEXT: br label [[TMP12]]
120+
; ARM: 12:
121+
; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
122+
; ARM-NEXT: ret i1 [[TMP13]]
123+
;
90124
%x = call i1 @llvm.type.test(ptr %p, metadata !"bytearray7")
91125
ret i1 %x
92126
}
93127

94-
; CHECK: define i1 @bytearray32(ptr [[p:%.*]])
95128
define i1 @bytearray32(ptr %p) {
96-
; CHECK-NEXT: [[pi:%.*]] = ptrtoint ptr [[p]] to i64
97-
; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
98-
; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (ptr @__typeid_bytearray32_align to i8) to i64)
99-
; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray32_align to i8)) to i64)
100-
; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 4
101-
; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 60
102-
; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
103-
; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
104-
; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 12346
105-
; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
106-
107-
; CHECK: [[t]]:
108-
; CHECK-NEXT: [[gep:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[or]]
109-
; CHECK-NEXT: [[load:%.*]] = load i8, ptr [[gep]]
110-
; X86-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
111-
; ARM-NEXT: [[and:%.*]] = and i8 [[load]], ptrtoint (ptr inttoptr (i64 128 to ptr) to i8)
112-
; CHECK-NEXT: [[ne:%.*]] = icmp ne i8 [[and]], 0
113-
; CHECK-NEXT: br label %[[f]]
114-
115-
; CHECK: [[f]]:
116-
; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
117-
; CHECK-NEXT: ret i1 [[phi]]
129+
; X86-LABEL: define i1 @bytearray32(
130+
; X86-SAME: ptr [[P:%.*]]) {
131+
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
132+
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
133+
; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_bytearray32_align to i8) to i64)
134+
; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_bytearray32_align to i8)) to i64)
135+
; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
136+
; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
137+
; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
138+
; X86: 7:
139+
; X86-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP5]]
140+
; X86-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
141+
; X86-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
142+
; X86-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
143+
; X86-NEXT: br label [[TMP12]]
144+
; X86: 12:
145+
; X86-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
146+
; X86-NEXT: ret i1 [[TMP13]]
147+
;
148+
; ARM-LABEL: define i1 @bytearray32(
149+
; ARM-SAME: ptr [[P:%.*]]) {
150+
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
151+
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_bytearray32_global_addr to i64)
152+
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 4
153+
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 60
154+
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
155+
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 12346
156+
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
157+
; ARM: 7:
158+
; ARM-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP5]]
159+
; ARM-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
160+
; ARM-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr inttoptr (i64 128 to ptr) to i8)
161+
; ARM-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
162+
; ARM-NEXT: br label [[TMP12]]
163+
; ARM: 12:
164+
; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
165+
; ARM-NEXT: ret i1 [[TMP13]]
166+
;
118167
%x = call i1 @llvm.type.test(ptr %p, metadata !"bytearray32")
119168
ret i1 %x
120169
}
121170

122-
; CHECK: define i1 @inline5(ptr [[p:%.*]])
123171
define i1 @inline5(ptr %p) {
124-
; CHECK-NEXT: [[pi:%.*]] = ptrtoint ptr [[p]] to i64
125-
; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
126-
; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (ptr @__typeid_inline5_align to i8) to i64)
127-
; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline5_align to i8)) to i64)
128-
; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 5
129-
; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 59
130-
; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
131-
; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
132-
; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 31
133-
; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
134-
135-
; CHECK: [[t]]:
136-
; CHECK-NEXT: [[trunc:%.*]] = trunc i64 [[or]] to i32
137-
; CHECK-NEXT: [[and:%.*]] = and i32 [[trunc]], 31
138-
; CHECK-NEXT: [[shl2:%.*]] = shl i32 1, [[and]]
139-
; X86-NEXT: [[and2:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[shl2]]
140-
; ARM-NEXT: [[and2:%.*]] = and i32 123, [[shl2]]
141-
; CHECK-NEXT: [[ne:%.*]] = icmp ne i32 [[and2]], 0
142-
; CHECK-NEXT: br label %[[f]]
143-
144-
; CHECK: [[f]]:
145-
; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
146-
; CHECK-NEXT: ret i1 [[phi]]
172+
; X86-LABEL: define i1 @inline5(
173+
; X86-SAME: ptr [[P:%.*]]) {
174+
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
175+
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
176+
; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_inline5_align to i8) to i64)
177+
; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline5_align to i8)) to i64)
178+
; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
179+
; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
180+
; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]]
181+
; X86: 7:
182+
; X86-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP5]] to i32
183+
; X86-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 31
184+
; X86-NEXT: [[TMP10:%.*]] = shl i32 1, [[TMP9]]
185+
; X86-NEXT: [[TMP11:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP10]]
186+
; X86-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
187+
; X86-NEXT: br label [[TMP13]]
188+
; X86: 13:
189+
; X86-NEXT: [[TMP14:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP12]], [[TMP7]] ]
190+
; X86-NEXT: ret i1 [[TMP14]]
191+
;
192+
; ARM-LABEL: define i1 @inline5(
193+
; ARM-SAME: ptr [[P:%.*]]) {
194+
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
195+
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline5_global_addr to i64)
196+
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 5
197+
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 59
198+
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
199+
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 31
200+
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]]
201+
; ARM: 7:
202+
; ARM-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP5]] to i32
203+
; ARM-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 31
204+
; ARM-NEXT: [[TMP10:%.*]] = shl i32 1, [[TMP9]]
205+
; ARM-NEXT: [[TMP11:%.*]] = and i32 123, [[TMP10]]
206+
; ARM-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
207+
; ARM-NEXT: br label [[TMP13]]
208+
; ARM: 13:
209+
; ARM-NEXT: [[TMP14:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP12]], [[TMP7]] ]
210+
; ARM-NEXT: ret i1 [[TMP14]]
211+
;
147212
%x = call i1 @llvm.type.test(ptr %p, metadata !"inline5")
148213
ret i1 %x
149214
}
150215

151-
; CHECK: define i1 @inline6(ptr [[p:%.*]])
152216
define i1 @inline6(ptr %p) {
153-
; CHECK-NEXT: [[pi:%.*]] = ptrtoint ptr [[p]] to i64
154-
; CHECK-NEXT: [[sub:%.*]] = sub i64 [[pi]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
155-
; X86-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], zext (i8 ptrtoint (ptr @__typeid_inline6_align to i8) to i64)
156-
; X86-NEXT: [[shl:%.*]] = shl i64 [[sub]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline6_align to i8)) to i64)
157-
; ARM-NEXT: [[lshr:%.*]] = lshr i64 [[sub]], 6
158-
; ARM-NEXT: [[shl:%.*]] = shl i64 [[sub]], 58
159-
; CHECK-NEXT: [[or:%.*]] = or i64 [[lshr]], [[shl]]
160-
; X86-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
161-
; ARM-NEXT: [[ule:%.*]] = icmp ule i64 [[or]], 63
162-
; CHECK-NEXT: br i1 [[ule]], label %[[t:.*]], label %[[f:.*]]
163-
164-
; CHECK: [[t]]:
165-
; CHECK-NEXT: [[and:%.*]] = and i64 [[or]], 63
166-
; CHECK-NEXT: [[shl2:%.*]] = shl i64 1, [[and]]
167-
; X86-NEXT: [[and2:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[shl2]]
168-
; ARM-NEXT: [[and2:%.*]] = and i64 1000000000000, [[shl2]]
169-
; CHECK-NEXT: [[ne:%.*]] = icmp ne i64 [[and2]], 0
170-
; CHECK-NEXT: br label %[[f]]
171-
172-
; CHECK: [[f]]:
173-
; CHECK-NEXT: [[phi:%.*]] = phi i1 [ false, %0 ], [ [[ne]], %[[t]] ]
174-
; CHECK-NEXT: ret i1 [[phi]]
217+
; X86-LABEL: define i1 @inline6(
218+
; X86-SAME: ptr [[P:%.*]]) {
219+
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
220+
; X86-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
221+
; X86-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], zext (i8 ptrtoint (ptr @__typeid_inline6_align to i8) to i64)
222+
; X86-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], zext (i8 sub (i8 64, i8 ptrtoint (ptr @__typeid_inline6_align to i8)) to i64)
223+
; X86-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
224+
; X86-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
225+
; X86-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
226+
; X86: 7:
227+
; X86-NEXT: [[TMP8:%.*]] = and i64 [[TMP5]], 63
228+
; X86-NEXT: [[TMP9:%.*]] = shl i64 1, [[TMP8]]
229+
; X86-NEXT: [[TMP10:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP9]]
230+
; X86-NEXT: [[TMP11:%.*]] = icmp ne i64 [[TMP10]], 0
231+
; X86-NEXT: br label [[TMP12]]
232+
; X86: 12:
233+
; X86-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
234+
; X86-NEXT: ret i1 [[TMP13]]
235+
;
236+
; ARM-LABEL: define i1 @inline6(
237+
; ARM-SAME: ptr [[P:%.*]]) {
238+
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
239+
; ARM-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], ptrtoint (ptr @__typeid_inline6_global_addr to i64)
240+
; ARM-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 6
241+
; ARM-NEXT: [[TMP4:%.*]] = shl i64 [[TMP2]], 58
242+
; ARM-NEXT: [[TMP5:%.*]] = or i64 [[TMP3]], [[TMP4]]
243+
; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 63
244+
; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
245+
; ARM: 7:
246+
; ARM-NEXT: [[TMP8:%.*]] = and i64 [[TMP5]], 63
247+
; ARM-NEXT: [[TMP9:%.*]] = shl i64 1, [[TMP8]]
248+
; ARM-NEXT: [[TMP10:%.*]] = and i64 1000000000000, [[TMP9]]
249+
; ARM-NEXT: [[TMP11:%.*]] = icmp ne i64 [[TMP10]], 0
250+
; ARM-NEXT: br label [[TMP12]]
251+
; ARM: 12:
252+
; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
253+
; ARM-NEXT: ret i1 [[TMP13]]
254+
;
175255
%x = call i1 @llvm.type.test(ptr %p, metadata !"inline6")
176256
ret i1 %x
177257
}
178258

179-
; CHECK: define i1 @single(ptr [[p:%.*]])
180259
define i1 @single(ptr %p) {
181-
; CHECK-NEXT: [[pi:%.*]] = ptrtoint ptr [[p]] to i64
182-
; CHECK-NEXT: [[eq:%.*]] = icmp eq i64 [[pi]], ptrtoint (ptr @__typeid_single_global_addr to i64)
183-
; CHECK-NEXT: ret i1 [[eq]]
260+
; CHECK-LABEL: define i1 @single(
261+
; CHECK-SAME: ptr [[P:%.*]]) {
262+
; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
263+
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], ptrtoint (ptr @__typeid_single_global_addr to i64)
264+
; CHECK-NEXT: ret i1 [[TMP2]]
265+
;
184266
%x = call i1 @llvm.type.test(ptr %p, metadata !"single")
185267
ret i1 %x
186268
}

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