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AMDGPU: Make use of default operands
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+23
-27
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2 files changed

+23
-27
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‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 22 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -779,14 +779,14 @@ def : RsqPat<V_RSQ_F64_e32, f64>;
779779
def : GCNPat <
780780
(f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
781781
(f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
782-
(V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
782+
(V_FRACT_F32_e64 $mods, $x)
783783
>;
784784

785785
// Convert (x + (-floor(x))) to fract(x)
786786
def : GCNPat <
787787
(f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
788788
(f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
789-
(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)
789+
(V_FRACT_F64_e64 $mods, $x)
790790
>;
791791

792792
} // End OtherPredicates = [UnsafeFPMath]
@@ -795,27 +795,27 @@ def : GCNPat <
795795
// f16_to_fp patterns
796796
def : GCNPat <
797797
(f32 (f16_to_fp i32:$src0)),
798-
(V_CVT_F32_F16_e64 SRCMODS.NONE, $src0, DSTCLAMP.NONE, DSTOMOD.NONE)
798+
(V_CVT_F32_F16_e64 SRCMODS.NONE, $src0)
799799
>;
800800

801801
def : GCNPat <
802802
(f32 (f16_to_fp (and_oneuse i32:$src0, 0x7fff))),
803-
(V_CVT_F32_F16_e64 SRCMODS.ABS, $src0, DSTCLAMP.NONE, DSTOMOD.NONE)
803+
(V_CVT_F32_F16_e64 SRCMODS.ABS, $src0)
804804
>;
805805

806806
def : GCNPat <
807807
(f32 (f16_to_fp (i32 (srl_oneuse (and_oneuse i32:$src0, 0x7fff0000), (i32 16))))),
808-
(V_CVT_F32_F16_e64 SRCMODS.ABS, (i32 (V_LSHRREV_B32_e64 (i32 16), i32:$src0)), DSTCLAMP.NONE, DSTOMOD.NONE)
808+
(V_CVT_F32_F16_e64 SRCMODS.ABS, (i32 (V_LSHRREV_B32_e64 (i32 16), i32:$src0)))
809809
>;
810810

811811
def : GCNPat <
812812
(f32 (f16_to_fp (or_oneuse i32:$src0, 0x8000))),
813-
(V_CVT_F32_F16_e64 SRCMODS.NEG_ABS, $src0, DSTCLAMP.NONE, DSTOMOD.NONE)
813+
(V_CVT_F32_F16_e64 SRCMODS.NEG_ABS, $src0)
814814
>;
815815

816816
def : GCNPat <
817817
(f32 (f16_to_fp (xor_oneuse i32:$src0, 0x8000))),
818-
(V_CVT_F32_F16_e64 SRCMODS.NEG, $src0, DSTCLAMP.NONE, DSTOMOD.NONE)
818+
(V_CVT_F32_F16_e64 SRCMODS.NEG, $src0)
819819
>;
820820

821821
def : GCNPat <
@@ -826,7 +826,7 @@ def : GCNPat <
826826
// fp_to_fp16 patterns
827827
def : GCNPat <
828828
(i32 (AMDGPUfp_to_f16 (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))),
829-
(V_CVT_F16_F32_e64 $src0_modifiers, f32:$src0, DSTCLAMP.NONE, DSTOMOD.NONE)
829+
(V_CVT_F16_F32_e64 $src0_modifiers, f32:$src0)
830830
>;
831831

832832
def : GCNPat <
@@ -1870,12 +1870,12 @@ def : GCNPat <
18701870
let OtherPredicates = [NoFP16Denormals] in {
18711871
def : GCNPat<
18721872
(fcanonicalize (f16 (VOP3Mods f16:$src, i32:$src_mods))),
1873-
(V_MUL_F16_e64 0, (i32 CONST.FP16_ONE), $src_mods, $src, 0, 0)
1873+
(V_MUL_F16_e64 0, (i32 CONST.FP16_ONE), $src_mods, $src)
18741874
>;
18751875

18761876
def : GCNPat<
18771877
(fcanonicalize (f16 (fneg (VOP3Mods f16:$src, i32:$src_mods)))),
1878-
(V_MUL_F16_e64 0, (i32 CONST.FP16_NEG_ONE), $src_mods, $src, 0, 0)
1878+
(V_MUL_F16_e64 0, (i32 CONST.FP16_NEG_ONE), $src_mods, $src)
18791879
>;
18801880

18811881
def : GCNPat<
@@ -1901,53 +1901,53 @@ def : GCNPat<
19011901
let OtherPredicates = [NoFP32Denormals] in {
19021902
def : GCNPat<
19031903
(fcanonicalize (f32 (VOP3Mods f32:$src, i32:$src_mods))),
1904-
(V_MUL_F32_e64 0, (i32 CONST.FP32_ONE), $src_mods, $src, 0, 0)
1904+
(V_MUL_F32_e64 0, (i32 CONST.FP32_ONE), $src_mods, $src)
19051905
>;
19061906

19071907
def : GCNPat<
19081908
(fcanonicalize (f32 (fneg (VOP3Mods f32:$src, i32:$src_mods)))),
1909-
(V_MUL_F32_e64 0, (i32 CONST.FP32_NEG_ONE), $src_mods, $src, 0, 0)
1909+
(V_MUL_F32_e64 0, (i32 CONST.FP32_NEG_ONE), $src_mods, $src)
19101910
>;
19111911
}
19121912

19131913
let OtherPredicates = [FP32Denormals] in {
19141914
def : GCNPat<
19151915
(fcanonicalize (f32 (VOP3Mods f32:$src, i32:$src_mods))),
1916-
(V_MAX_F32_e64 $src_mods, $src, $src_mods, $src, 0, 0)
1916+
(V_MAX_F32_e64 $src_mods, $src, $src_mods, $src)
19171917
>;
19181918
}
19191919

19201920
let OtherPredicates = [NoFP64Denormals] in {
19211921
def : GCNPat<
19221922
(fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))),
1923-
(V_MUL_F64 0, CONST.FP64_ONE, $src_mods, $src, 0, 0)
1923+
(V_MUL_F64 0, CONST.FP64_ONE, $src_mods, $src)
19241924
>;
19251925
}
19261926

19271927
let OtherPredicates = [FP64Denormals] in {
19281928
def : GCNPat<
19291929
(fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))),
1930-
(V_MAX_F64 $src_mods, $src, $src_mods, $src, 0, 0)
1930+
(V_MAX_F64 $src_mods, $src, $src_mods, $src)
19311931
>;
19321932
}
19331933

19341934
let OtherPredicates = [HasDLInsts] in {
19351935
def : GCNPat <
1936-
(fma (f32 (VOP3Mods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1936+
(fma (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)),
19371937
(f32 (VOP3Mods f32:$src1, i32:$src1_modifiers)),
19381938
(f32 (VOP3NoMods f32:$src2))),
19391939
(V_FMAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
1940-
SRCMODS.NONE, $src2, $clamp, $omod)
1940+
SRCMODS.NONE, $src2)
19411941
>;
19421942
} // End OtherPredicates = [HasDLInsts]
19431943

19441944
let SubtargetPredicate = isGFX10Plus in
19451945
def : GCNPat <
1946-
(fma (f16 (VOP3Mods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1946+
(fma (f16 (VOP3Mods f32:$src0, i32:$src0_modifiers)),
19471947
(f16 (VOP3Mods f32:$src1, i32:$src1_modifiers)),
19481948
(f16 (VOP3NoMods f32:$src2))),
19491949
(V_FMAC_F16_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
1950-
SRCMODS.NONE, $src2, $clamp, $omod)
1950+
SRCMODS.NONE, $src2)
19511951
>;
19521952

19531953
// COPY is workaround tablegen bug from multiple outputs
@@ -2075,13 +2075,11 @@ def : GCNPat <
20752075
(V_CNDMASK_B64_PSEUDO
20762076
(V_MIN_F64
20772077
SRCMODS.NONE,
2078-
(V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
2078+
(V_FRACT_F64_e64 $mods, $x),
20792079
SRCMODS.NONE,
2080-
(V_MOV_B64_PSEUDO 0x3fefffffffffffff),
2081-
DSTCLAMP.NONE, DSTOMOD.NONE),
2080+
(V_MOV_B64_PSEUDO 0x3fefffffffffffff)),
20822081
$x,
2083-
(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, (i32 3 /*NaN*/))),
2084-
DSTCLAMP.NONE, DSTOMOD.NONE)
2082+
(V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, (i32 3 /*NaN*/))))
20852083
>;
20862084

20872085
} // End SubtargetPredicates = isGFX6

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -89,9 +89,7 @@ class VOP1_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
8989
class getVOP1Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
9090
list<dag> ret =
9191
!if(P.HasModifiers,
92-
[(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
93-
i32:$src0_modifiers,
94-
i1:$clamp, i32:$omod))))],
92+
[(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
9593
!if(P.HasOMod,
9694
[(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
9795
i1:$clamp, i32:$omod))))],

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