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[VectorCombine] Fix trunc generated between PHINodes (#108228)
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2 files changed

+33
-2
lines changed

2 files changed

+33
-2
lines changed

llvm/lib/Transforms/Vectorize/VectorCombine.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2652,8 +2652,12 @@ bool VectorCombine::shrinkType(llvm::Instruction &I) {
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return false;
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Value *Op0 = ZExted;
2655-
if (auto *OI = dyn_cast<Instruction>(OtherOperand))
2656-
Builder.SetInsertPoint(OI->getNextNode());
2655+
if (auto *OI = dyn_cast<Instruction>(OtherOperand)) {
2656+
if (isa<PHINode>(OI))
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Builder.SetInsertPoint(OI->getParent()->getFirstInsertionPt());
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else
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Builder.SetInsertPoint(OI->getNextNode());
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}
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Value *Op1 = Builder.CreateTrunc(OtherOperand, SmallTy);
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Builder.SetInsertPoint(&I);
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// Keep the order of operands the same

llvm/test/Transforms/VectorCombine/AArch64/shrink-types.ll

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,4 +73,31 @@ entry:
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ret i32 %6
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}
7575

76+
define i32 @phi_bug(<16 x i32> %a, ptr %b) {
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; CHECK-LABEL: @phi_bug(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[B:%.*]], align 1
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
81+
; CHECK: vector.body:
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; CHECK-NEXT: [[A_PHI:%.*]] = phi <16 x i32> [ [[A:%.*]], [[ENTRY:%.*]] ]
83+
; CHECK-NEXT: [[WIDE_LOAD_PHI:%.*]] = phi <16 x i8> [ [[WIDE_LOAD]], [[ENTRY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = trunc <16 x i32> [[A_PHI]] to <16 x i8>
85+
; CHECK-NEXT: [[TMP1:%.*]] = and <16 x i8> [[WIDE_LOAD_PHI]], [[TMP0]]
86+
; CHECK-NEXT: [[TMP2:%.*]] = zext <16 x i8> [[TMP1]] to <16 x i32>
87+
; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP2]])
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; CHECK-NEXT: ret i32 [[TMP3]]
89+
;
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entry:
91+
%wide.load = load <16 x i8>, ptr %b, align 1
92+
br label %vector.body
93+
94+
vector.body:
95+
%a.phi = phi <16 x i32> [ %a, %entry ]
96+
%wide.load.phi = phi <16 x i8> [ %wide.load, %entry ]
97+
%0 = zext <16 x i8> %wide.load.phi to <16 x i32>
98+
%1 = and <16 x i32> %0, %a.phi
99+
%2 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %1)
100+
ret i32 %2
101+
}
102+
76103
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)

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