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[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
Reviewed By: frasercrmck, arcbbb Differential Revision: https://reviews.llvm.org/D97408
1 parent 03b7bc0 commit 95c6824

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8 files changed

+56
-289
lines changed

8 files changed

+56
-289
lines changed

‎llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp

Lines changed: 56 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,56 @@ char RISCVCleanupVSETVLI::ID = 0;
5252
INITIALIZE_PASS(RISCVCleanupVSETVLI, DEBUG_TYPE,
5353
RISCV_CLEANUP_VSETVLI_NAME, false, false)
5454

55+
static bool isRedundantVSETVLI(MachineInstr &MI, MachineInstr *PrevVSETVLI) {
56+
// If we don't have a previous VSET{I}VLI or the VL output isn't dead, we
57+
// can't remove this VSETVLI.
58+
if (!PrevVSETVLI || !MI.getOperand(0).isDead())
59+
return false;
60+
61+
// Does this VSET{I}VLI use the same VTYPE immediate.
62+
int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm();
63+
int64_t VTYPEImm = MI.getOperand(2).getImm();
64+
if (PrevVTYPEImm != VTYPEImm)
65+
return false;
66+
67+
if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
68+
// If the previous opcode wasn't vsetivli we can't compare them.
69+
if (PrevVSETVLI->getOpcode() != RISCV::PseudoVSETIVLI)
70+
return false;
71+
72+
// For VSETIVLI, we can just compare the immediates.
73+
return PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm();
74+
}
75+
76+
assert(MI.getOpcode() == RISCV::PseudoVSETVLI);
77+
Register AVLReg = MI.getOperand(1).getReg();
78+
79+
// If this VSETVLI isn't changing VL, it is redundant.
80+
if (AVLReg == RISCV::X0 && MI.getOperand(0).getReg() == RISCV::X0)
81+
return true;
82+
83+
// If the previous opcode isn't vsetvli we can't do any more comparison.
84+
if (PrevVSETVLI->getOpcode() != RISCV::PseudoVSETVLI)
85+
return false;
86+
87+
// Does this VSETVLI use the same AVL register?
88+
if (AVLReg != PrevVSETVLI->getOperand(1).getReg())
89+
return false;
90+
91+
// If the AVLReg is X0 we must be setting VL to VLMAX. Keeping VL unchanged
92+
// was handled above.
93+
if (AVLReg == RISCV::X0) {
94+
// This instruction is setting VL to VLMAX, this is redundant if the
95+
// previous VSETVLI was also setting VL to VLMAX. But it is not redundant
96+
// if they were setting it to any other value or leaving VL unchanged.
97+
Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg();
98+
return PrevOutVL != RISCV::X0;
99+
}
100+
101+
// This vsetvli is redundant.
102+
return true;
103+
}
104+
55105
bool RISCVCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
56106
bool Changed = false;
57107
MachineInstr *PrevVSETVLI = nullptr;
@@ -70,62 +120,14 @@ bool RISCVCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
70120
continue;
71121
}
72122

73-
// If we don't have a previous VSET{I}VLI or the VL output isn't dead, we
74-
// can't remove this VSETVLI.
75-
if (!PrevVSETVLI || !MI.getOperand(0).isDead()) {
76-
PrevVSETVLI = &MI;
77-
continue;
78-
}
79-
80-
// If a previous "set vl" instruction opcode is different from this one, we
81-
// can't differentiate the AVL values.
82-
if (PrevVSETVLI->getOpcode() != MI.getOpcode()) {
83-
PrevVSETVLI = &MI;
84-
continue;
85-
}
86-
87-
// The remaining two cases are
88-
// 1. PrevVSETVLI = PseudoVSETVLI
89-
// MI = PseudoVSETVLI
90-
//
91-
// 2. PrevVSETVLI = PseudoVSETIVLI
92-
// MI = PseudoVSETIVLI
93-
Register AVLReg;
94-
bool SameAVL = false;
95-
if (MI.getOpcode() == RISCV::PseudoVSETVLI) {
96-
AVLReg = MI.getOperand(1).getReg();
97-
SameAVL = PrevVSETVLI->getOperand(1).getReg() == AVLReg;
98-
} else { // RISCV::PseudoVSETIVLI
99-
SameAVL =
100-
PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm();
101-
}
102-
int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm();
103-
int64_t VTYPEImm = MI.getOperand(2).getImm();
104-
105-
// Does this VSET{I}VLI use the same AVL register/value and VTYPE immediate?
106-
if (!SameAVL || PrevVTYPEImm != VTYPEImm) {
123+
if (isRedundantVSETVLI(MI, PrevVSETVLI)) {
124+
// This VSETVLI is redundant, remove it.
125+
MI.eraseFromParent();
126+
Changed = true;
127+
} else {
128+
// Otherwise update VSET{I}VLI for the next iteration.
107129
PrevVSETVLI = &MI;
108-
continue;
109130
}
110-
111-
// If the AVLReg is X0 we need to look at the output VL of both VSETVLIs.
112-
if ((MI.getOpcode() == RISCV::PseudoVSETVLI) && (AVLReg == RISCV::X0)) {
113-
assert((PrevVSETVLI->getOpcode() == RISCV::PseudoVSETVLI) &&
114-
"Unexpected vsetvli opcode.");
115-
Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg();
116-
Register OutVL = MI.getOperand(0).getReg();
117-
// We can't remove if the previous VSETVLI left VL unchanged and the
118-
// current instruction is setting it to VLMAX. Without knowing the VL
119-
// before the previous instruction we don't know if this is a change.
120-
if (PrevOutVL == RISCV::X0 && OutVL != RISCV::X0) {
121-
PrevVSETVLI = &MI;
122-
continue;
123-
}
124-
}
125-
126-
// This VSETVLI is redundant, remove it.
127-
MI.eraseFromParent();
128-
Changed = true;
129131
}
130132

131133
return Changed;

‎llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@ define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
1717
; CHECK: # %bb.0:
1818
; CHECK-NEXT: vsetivli a0, 1, e16,mf4,ta,mu
1919
; CHECK-NEXT: vslidedown.vi v25, v8, 2
20-
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
2120
; CHECK-NEXT: vfmv.f.s fa0, v25
2221
; CHECK-NEXT: ret
2322
%r = extractelement <vscale x 1 x half> %v, i32 2
@@ -29,7 +28,6 @@ define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 %idx) {
2928
; CHECK: # %bb.0:
3029
; CHECK-NEXT: vsetivli a1, 1, e16,mf4,ta,mu
3130
; CHECK-NEXT: vslidedown.vx v25, v8, a0
32-
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
3331
; CHECK-NEXT: vfmv.f.s fa0, v25
3432
; CHECK-NEXT: ret
3533
%r = extractelement <vscale x 1 x half> %v, i32 %idx
@@ -51,7 +49,6 @@ define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
5149
; CHECK: # %bb.0:
5250
; CHECK-NEXT: vsetivli a0, 1, e16,mf2,ta,mu
5351
; CHECK-NEXT: vslidedown.vi v25, v8, 2
54-
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
5552
; CHECK-NEXT: vfmv.f.s fa0, v25
5653
; CHECK-NEXT: ret
5754
%r = extractelement <vscale x 2 x half> %v, i32 2
@@ -63,7 +60,6 @@ define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 %idx) {
6360
; CHECK: # %bb.0:
6461
; CHECK-NEXT: vsetivli a1, 1, e16,mf2,ta,mu
6562
; CHECK-NEXT: vslidedown.vx v25, v8, a0
66-
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
6763
; CHECK-NEXT: vfmv.f.s fa0, v25
6864
; CHECK-NEXT: ret
6965
%r = extractelement <vscale x 2 x half> %v, i32 %idx
@@ -85,7 +81,6 @@ define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
8581
; CHECK: # %bb.0:
8682
; CHECK-NEXT: vsetivli a0, 1, e16,m1,ta,mu
8783
; CHECK-NEXT: vslidedown.vi v25, v8, 2
88-
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
8984
; CHECK-NEXT: vfmv.f.s fa0, v25
9085
; CHECK-NEXT: ret
9186
%r = extractelement <vscale x 4 x half> %v, i32 2
@@ -97,7 +92,6 @@ define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 %idx) {
9792
; CHECK: # %bb.0:
9893
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
9994
; CHECK-NEXT: vslidedown.vx v25, v8, a0
100-
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
10195
; CHECK-NEXT: vfmv.f.s fa0, v25
10296
; CHECK-NEXT: ret
10397
%r = extractelement <vscale x 4 x half> %v, i32 %idx
@@ -119,7 +113,6 @@ define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
119113
; CHECK: # %bb.0:
120114
; CHECK-NEXT: vsetivli a0, 1, e16,m2,ta,mu
121115
; CHECK-NEXT: vslidedown.vi v26, v8, 2
122-
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
123116
; CHECK-NEXT: vfmv.f.s fa0, v26
124117
; CHECK-NEXT: ret
125118
%r = extractelement <vscale x 8 x half> %v, i32 2
@@ -131,7 +124,6 @@ define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 %idx) {
131124
; CHECK: # %bb.0:
132125
; CHECK-NEXT: vsetivli a1, 1, e16,m2,ta,mu
133126
; CHECK-NEXT: vslidedown.vx v26, v8, a0
134-
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
135127
; CHECK-NEXT: vfmv.f.s fa0, v26
136128
; CHECK-NEXT: ret
137129
%r = extractelement <vscale x 8 x half> %v, i32 %idx
@@ -153,7 +145,6 @@ define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
153145
; CHECK: # %bb.0:
154146
; CHECK-NEXT: vsetivli a0, 1, e16,m4,ta,mu
155147
; CHECK-NEXT: vslidedown.vi v28, v8, 2
156-
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
157148
; CHECK-NEXT: vfmv.f.s fa0, v28
158149
; CHECK-NEXT: ret
159150
%r = extractelement <vscale x 16 x half> %v, i32 2
@@ -165,7 +156,6 @@ define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 %idx) {
165156
; CHECK: # %bb.0:
166157
; CHECK-NEXT: vsetivli a1, 1, e16,m4,ta,mu
167158
; CHECK-NEXT: vslidedown.vx v28, v8, a0
168-
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
169159
; CHECK-NEXT: vfmv.f.s fa0, v28
170160
; CHECK-NEXT: ret
171161
%r = extractelement <vscale x 16 x half> %v, i32 %idx
@@ -187,7 +177,6 @@ define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) {
187177
; CHECK: # %bb.0:
188178
; CHECK-NEXT: vsetivli a0, 1, e16,m8,ta,mu
189179
; CHECK-NEXT: vslidedown.vi v8, v8, 2
190-
; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu
191180
; CHECK-NEXT: vfmv.f.s fa0, v8
192181
; CHECK-NEXT: ret
193182
%r = extractelement <vscale x 32 x half> %v, i32 2
@@ -199,7 +188,6 @@ define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 %idx) {
199188
; CHECK: # %bb.0:
200189
; CHECK-NEXT: vsetivli a1, 1, e16,m8,ta,mu
201190
; CHECK-NEXT: vslidedown.vx v8, v8, a0
202-
; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu
203191
; CHECK-NEXT: vfmv.f.s fa0, v8
204192
; CHECK-NEXT: ret
205193
%r = extractelement <vscale x 32 x half> %v, i32 %idx
@@ -221,7 +209,6 @@ define float @extractelt_nxv1f32_imm(<vscale x 1 x float> %v) {
221209
; CHECK: # %bb.0:
222210
; CHECK-NEXT: vsetivli a0, 1, e32,mf2,ta,mu
223211
; CHECK-NEXT: vslidedown.vi v25, v8, 2
224-
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
225212
; CHECK-NEXT: vfmv.f.s fa0, v25
226213
; CHECK-NEXT: ret
227214
%r = extractelement <vscale x 1 x float> %v, i32 2
@@ -233,7 +220,6 @@ define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 %idx) {
233220
; CHECK: # %bb.0:
234221
; CHECK-NEXT: vsetivli a1, 1, e32,mf2,ta,mu
235222
; CHECK-NEXT: vslidedown.vx v25, v8, a0
236-
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
237223
; CHECK-NEXT: vfmv.f.s fa0, v25
238224
; CHECK-NEXT: ret
239225
%r = extractelement <vscale x 1 x float> %v, i32 %idx
@@ -255,7 +241,6 @@ define float @extractelt_nxv2f32_imm(<vscale x 2 x float> %v) {
255241
; CHECK: # %bb.0:
256242
; CHECK-NEXT: vsetivli a0, 1, e32,m1,ta,mu
257243
; CHECK-NEXT: vslidedown.vi v25, v8, 2
258-
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
259244
; CHECK-NEXT: vfmv.f.s fa0, v25
260245
; CHECK-NEXT: ret
261246
%r = extractelement <vscale x 2 x float> %v, i32 2
@@ -267,7 +252,6 @@ define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 %idx) {
267252
; CHECK: # %bb.0:
268253
; CHECK-NEXT: vsetivli a1, 1, e32,m1,ta,mu
269254
; CHECK-NEXT: vslidedown.vx v25, v8, a0
270-
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
271255
; CHECK-NEXT: vfmv.f.s fa0, v25
272256
; CHECK-NEXT: ret
273257
%r = extractelement <vscale x 2 x float> %v, i32 %idx
@@ -289,7 +273,6 @@ define float @extractelt_nxv4f32_imm(<vscale x 4 x float> %v) {
289273
; CHECK: # %bb.0:
290274
; CHECK-NEXT: vsetivli a0, 1, e32,m2,ta,mu
291275
; CHECK-NEXT: vslidedown.vi v26, v8, 2
292-
; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu
293276
; CHECK-NEXT: vfmv.f.s fa0, v26
294277
; CHECK-NEXT: ret
295278
%r = extractelement <vscale x 4 x float> %v, i32 2
@@ -301,7 +284,6 @@ define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 %idx) {
301284
; CHECK: # %bb.0:
302285
; CHECK-NEXT: vsetivli a1, 1, e32,m2,ta,mu
303286
; CHECK-NEXT: vslidedown.vx v26, v8, a0
304-
; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu
305287
; CHECK-NEXT: vfmv.f.s fa0, v26
306288
; CHECK-NEXT: ret
307289
%r = extractelement <vscale x 4 x float> %v, i32 %idx
@@ -323,7 +305,6 @@ define float @extractelt_nxv8f32_imm(<vscale x 8 x float> %v) {
323305
; CHECK: # %bb.0:
324306
; CHECK-NEXT: vsetivli a0, 1, e32,m4,ta,mu
325307
; CHECK-NEXT: vslidedown.vi v28, v8, 2
326-
; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu
327308
; CHECK-NEXT: vfmv.f.s fa0, v28
328309
; CHECK-NEXT: ret
329310
%r = extractelement <vscale x 8 x float> %v, i32 2
@@ -335,7 +316,6 @@ define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 %idx) {
335316
; CHECK: # %bb.0:
336317
; CHECK-NEXT: vsetivli a1, 1, e32,m4,ta,mu
337318
; CHECK-NEXT: vslidedown.vx v28, v8, a0
338-
; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu
339319
; CHECK-NEXT: vfmv.f.s fa0, v28
340320
; CHECK-NEXT: ret
341321
%r = extractelement <vscale x 8 x float> %v, i32 %idx
@@ -357,7 +337,6 @@ define float @extractelt_nxv16f32_imm(<vscale x 16 x float> %v) {
357337
; CHECK: # %bb.0:
358338
; CHECK-NEXT: vsetivli a0, 1, e32,m8,ta,mu
359339
; CHECK-NEXT: vslidedown.vi v8, v8, 2
360-
; CHECK-NEXT: vsetvli zero, zero, e32,m8,ta,mu
361340
; CHECK-NEXT: vfmv.f.s fa0, v8
362341
; CHECK-NEXT: ret
363342
%r = extractelement <vscale x 16 x float> %v, i32 2
@@ -369,7 +348,6 @@ define float @extractelt_nxv16f32_idx(<vscale x 16 x float> %v, i32 %idx) {
369348
; CHECK: # %bb.0:
370349
; CHECK-NEXT: vsetivli a1, 1, e32,m8,ta,mu
371350
; CHECK-NEXT: vslidedown.vx v8, v8, a0
372-
; CHECK-NEXT: vsetvli zero, zero, e32,m8,ta,mu
373351
; CHECK-NEXT: vfmv.f.s fa0, v8
374352
; CHECK-NEXT: ret
375353
%r = extractelement <vscale x 16 x float> %v, i32 %idx
@@ -391,7 +369,6 @@ define double @extractelt_nxv1f64_imm(<vscale x 1 x double> %v) {
391369
; CHECK: # %bb.0:
392370
; CHECK-NEXT: vsetivli a0, 1, e64,m1,ta,mu
393371
; CHECK-NEXT: vslidedown.vi v25, v8, 2
394-
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
395372
; CHECK-NEXT: vfmv.f.s fa0, v25
396373
; CHECK-NEXT: ret
397374
%r = extractelement <vscale x 1 x double> %v, i32 2
@@ -403,7 +380,6 @@ define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 %idx) {
403380
; CHECK: # %bb.0:
404381
; CHECK-NEXT: vsetivli a1, 1, e64,m1,ta,mu
405382
; CHECK-NEXT: vslidedown.vx v25, v8, a0
406-
; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
407383
; CHECK-NEXT: vfmv.f.s fa0, v25
408384
; CHECK-NEXT: ret
409385
%r = extractelement <vscale x 1 x double> %v, i32 %idx
@@ -425,7 +401,6 @@ define double @extractelt_nxv2f64_imm(<vscale x 2 x double> %v) {
425401
; CHECK: # %bb.0:
426402
; CHECK-NEXT: vsetivli a0, 1, e64,m2,ta,mu
427403
; CHECK-NEXT: vslidedown.vi v26, v8, 2
428-
; CHECK-NEXT: vsetvli zero, zero, e64,m2,ta,mu
429404
; CHECK-NEXT: vfmv.f.s fa0, v26
430405
; CHECK-NEXT: ret
431406
%r = extractelement <vscale x 2 x double> %v, i32 2
@@ -437,7 +412,6 @@ define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 %idx) {
437412
; CHECK: # %bb.0:
438413
; CHECK-NEXT: vsetivli a1, 1, e64,m2,ta,mu
439414
; CHECK-NEXT: vslidedown.vx v26, v8, a0
440-
; CHECK-NEXT: vsetvli zero, zero, e64,m2,ta,mu
441415
; CHECK-NEXT: vfmv.f.s fa0, v26
442416
; CHECK-NEXT: ret
443417
%r = extractelement <vscale x 2 x double> %v, i32 %idx
@@ -459,7 +433,6 @@ define double @extractelt_nxv4f64_imm(<vscale x 4 x double> %v) {
459433
; CHECK: # %bb.0:
460434
; CHECK-NEXT: vsetivli a0, 1, e64,m4,ta,mu
461435
; CHECK-NEXT: vslidedown.vi v28, v8, 2
462-
; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu
463436
; CHECK-NEXT: vfmv.f.s fa0, v28
464437
; CHECK-NEXT: ret
465438
%r = extractelement <vscale x 4 x double> %v, i32 2
@@ -471,7 +444,6 @@ define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 %idx) {
471444
; CHECK: # %bb.0:
472445
; CHECK-NEXT: vsetivli a1, 1, e64,m4,ta,mu
473446
; CHECK-NEXT: vslidedown.vx v28, v8, a0
474-
; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu
475447
; CHECK-NEXT: vfmv.f.s fa0, v28
476448
; CHECK-NEXT: ret
477449
%r = extractelement <vscale x 4 x double> %v, i32 %idx
@@ -493,7 +465,6 @@ define double @extractelt_nxv8f64_imm(<vscale x 8 x double> %v) {
493465
; CHECK: # %bb.0:
494466
; CHECK-NEXT: vsetivli a0, 1, e64,m8,ta,mu
495467
; CHECK-NEXT: vslidedown.vi v8, v8, 2
496-
; CHECK-NEXT: vsetvli zero, zero, e64,m8,ta,mu
497468
; CHECK-NEXT: vfmv.f.s fa0, v8
498469
; CHECK-NEXT: ret
499470
%r = extractelement <vscale x 8 x double> %v, i32 2
@@ -505,7 +476,6 @@ define double @extractelt_nxv8f64_idx(<vscale x 8 x double> %v, i32 %idx) {
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli a1, 1, e64,m8,ta,mu
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; CHECK-NEXT: vslidedown.vx v8, v8, a0
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; CHECK-NEXT: vsetvli zero, zero, e64,m8,ta,mu
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%r = extractelement <vscale x 8 x double> %v, i32 %idx

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