pre-commit test

Author: el-ev

llvm/test/Transforms/ConstraintElimination/uadd-usub-sat.ll

@@ -8,7 +8,9 @@ define i1 @uadd_sat_uge(i64 %a, i64 %b) {
 ; CHECK-LABEL: define i1 @uadd_sat_uge(
 ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
 ; CHECK-NEXT:    [[ADD_SAT:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]])
-; CHECK-NEXT:    [[CMP:%.*]] = and i1 true, true
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp uge i64 [[ADD_SAT]], [[A]]
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp uge i64 [[ADD_SAT]], [[B]]
+; CHECK-NEXT:    [[CMP:%.*]] = and i1 [[CMP1]], [[CMP2]]
 ; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %add.sat = call i64 @llvm.uadd.sat.i64(i64 %a, i64 %b)
@@ -22,13 +24,42 @@ define i1 @usub_sat_ule_lhs(i64 %a, i64 %b) {
 ; CHECK-LABEL: define i1 @usub_sat_ule_lhs(
 ; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
 ; CHECK-NEXT:    [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
-; CHECK-NEXT:    ret i1 true
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ule i64 [[SUB_SAT]], [[A]]
+; CHECK-NEXT:    ret i1 [[CMP]]
 ;
   %sub.sat = call i64 @llvm.usub.sat.i64(i64 %a, i64 %b)
   %cmp = icmp ule i64 %sub.sat, %a
   ret i1 %cmp
 }
 
+define i64 @usub_sat_when_lhs_ugt_rhs(i64 %a, i64 %b) {
+; CHECK-LABEL: define i64 @usub_sat_when_lhs_ugt_rhs(
+; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
+; CHECK-NEXT:    [[PRECOND:%.*]] = icmp ugt i64 [[A]], [[B]]
+; CHECK-NEXT:    call void @llvm.assume(i1 [[PRECOND]])
+; CHECK-NEXT:    [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
+; CHECK-NEXT:    ret i64 [[SUB_SAT]]
+;
+  %precond = icmp ugt i64 %a, %b
+  call void @llvm.assume(i1 %precond)
+  %sub.sat = call i64 @llvm.usub.sat.i64(i64 %a, i64 %b)
+  ret i64 %sub.sat
+}
+
+define i64 @usub_sat_when_lhs_ule_rhs(i64 %a, i64 %b) {
+; CHECK-LABEL: define i64 @usub_sat_when_lhs_ule_rhs(
+; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
+; CHECK-NEXT:    [[PRECOND:%.*]] = icmp ule i64 [[A]], [[B]]
+; CHECK-NEXT:    call void @llvm.assume(i1 [[PRECOND]])
+; CHECK-NEXT:    [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
+; CHECK-NEXT:    ret i64 [[SUB_SAT]]
+;
+  %precond = icmp ule i64 %a, %b
+  call void @llvm.assume(i1 %precond)
+  %sub.sat = call i64 @llvm.usub.sat.i64(i64 %a, i64 %b)
+  ret i64 %sub.sat
+}
+
 ; Negative test
 define i1 @usub_sat_not_ule_rhs(i64 %a, i64 %b) {
 ; CHECK-LABEL: define i1 @usub_sat_not_ule_rhs(
@@ -41,3 +72,13 @@ define i1 @usub_sat_not_ule_rhs(i64 %a, i64 %b) {
   %cmp = icmp ule i64 %sub.sat, %b
   ret i1 %cmp
 }
+
+define i64 @usub_sat_without_precond(i64 %a, i64 %b) {
+; CHECK-LABEL: define i64 @usub_sat_without_precond(
+; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) {
+; CHECK-NEXT:    [[SUB_SAT:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
+; CHECK-NEXT:    ret i64 [[SUB_SAT]]
+;
+  %sub.sat = call i64 @llvm.usub.sat.i64(i64 %a, i64 %b)
+  ret i64 %sub.sat
+}