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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 |
| 2 | +; RUN: opt -S -passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s |
| 3 | + |
| 4 | +define i32 @test(ptr %p) { |
| 5 | +; CHECK-LABEL: define i32 @test( |
| 6 | +; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] { |
| 7 | +; CHECK-NEXT: entry: |
| 8 | +; CHECK-NEXT: [[D_0:%.*]] = load i16, ptr [[P]], align 4 |
| 9 | +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[D_0]], i32 1 |
| 10 | +; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i16> [[TMP0]], zeroinitializer |
| 11 | +; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i16> [[TMP1]], zeroinitializer |
| 12 | +; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32> |
| 13 | +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, <4 x i32> <i32 4, i32 1, i32 6, i32 7> |
| 14 | +; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[TMP4]], zeroinitializer |
| 15 | +; CHECK-NEXT: [[TMP6:%.*]] = select <4 x i1> [[TMP5]], <4 x i16> [[TMP2]], <4 x i16> <i16 0, i16 2, i16 0, i16 0> |
| 16 | +; CHECK-NEXT: [[TMP7:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[TMP6]]) |
| 17 | +; CHECK-NEXT: [[TMP8:%.*]] = zext i16 [[TMP7]] to i32 |
| 18 | +; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP8]], i32 1) |
| 19 | +; CHECK-NEXT: ret i32 [[TMP9]] |
| 20 | +; |
| 21 | +entry: |
| 22 | + %d.0 = load i16, ptr %p, align 4 |
| 23 | + %zext.d.0 = zext i16 %d.0 to i32 |
| 24 | + %zero.0 = zext i16 0 to i32 |
| 25 | + %zero.1 = zext i16 0 to i32 |
| 26 | + %zero.2 = zext i16 0 to i32 |
| 27 | + |
| 28 | + %or.d.0 = or i32 %zext.d.0, 0 |
| 29 | + %or.zero.0 = or i32 %zero.0, 0 |
| 30 | + %or.zero.1 = or i32 %zero.1, 0 |
| 31 | + %or.zero.2 = or i32 %zero.2, 0 |
| 32 | + |
| 33 | + %zero.d.0 = and i32 %or.d.0, 0 |
| 34 | + %and.zero.0 = and i32 %or.zero.0, 0 |
| 35 | + %and.zero.1 = and i32 %or.zero.1, 0 |
| 36 | + %and.zero.2 = and i32 %or.zero.2, 0 |
| 37 | + |
| 38 | + %d.0.gt.0 = icmp sgt i32 %zext.d.0, 0 |
| 39 | + %false.0 = icmp sgt i32 0, 0 |
| 40 | + %false.1 = icmp sgt i32 0, 0 |
| 41 | + %false.2 = icmp sgt i32 0, 0 |
| 42 | + |
| 43 | + %select.0.2 = select i1 %d.0.gt.0, i32 %zero.d.0, i32 2 |
| 44 | + %select.1.0 = select i1 %false.0, i32 %and.zero.0, i32 0 |
| 45 | + %select.2.0 = select i1 %false.1, i32 %and.zero.1, i32 0 |
| 46 | + %select.3.0 = select i1 %false.2, i32 %and.zero.2, i32 0 |
| 47 | + |
| 48 | + %max.0 = call i32 @llvm.umax.i32(i32 %select.0.2, i32 %select.1.0) |
| 49 | + %max.1 = call i32 @llvm.umax.i32(i32 %max.0, i32 %select.2.0) |
| 50 | + %max.2 = call i32 @llvm.umax.i32(i32 %max.1, i32 %select.3.0) |
| 51 | + %max.3 = call i32 @llvm.umax.i32(i32 %max.2, i32 1) |
| 52 | + |
| 53 | + ret i32 %max.3 |
| 54 | +} |
| 55 | + |
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