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[Hexagon] Flip subreg bit for reverse pairs hvx .new (#75873)
In .new instructions, the upper vector of a reverse pair (e.g. V4 in V4:5) should be referenced with an odd sss value.
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-2
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3 files changed

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llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

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@@ -512,6 +512,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
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const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
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const unsigned ProdPairIndex =
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Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
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if (Rev)
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SubregBit = !SubregBit;
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Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
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} else if (SubregBit)
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// Hexagon PRM 10.11 New-value operands

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

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@@ -1036,8 +1036,10 @@ unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
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unsigned Producer2) {
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// If we're a single vector consumer of a double producer, set subreg bit
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// based on if we're accessing the lower or upper register component
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if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer))
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return (Consumer - Hexagon::V0) & 0x1;
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if (IsVecRegPair(Producer) && IsVecRegSingle(Consumer)) {
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unsigned Rev = IsReverseVecRegPair(Producer);
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return ((Consumer - Hexagon::V0) & 0x1) ^ Rev;
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}
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if (Producer2 != Hexagon::NoRegister)
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return Consumer == Producer;
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return 0;
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@@ -0,0 +1,18 @@
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# RUN: llvm-mc -triple=hexagon -mv69 -mhvx -filetype=obj %s | \
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# RUN: llvm-objdump --triple=hexagon --mcpu=hexagonv69 --mattr=+hvx -d - | \
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# RUN: FileCheck %s
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# CHECK: 00000000 <.text>:
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{
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V4:5.w = vadd(V1:0.w, V3:2.w)
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vmem(r0+#0) = v4.new
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}
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# CHECK-NEXT: 1c6240c5 { v4:5.w = vadd(v1:0.w,v3:2.w)
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# CHECK-NEXT: 2820c023 vmem(r0+#0x0) = v4.new }
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{
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V4:5.w = vadd(V1:0.w, V3:2.w)
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vmem(r0+#0) = v5.new
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}
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# CHECK-NEXT: 1c6240c5 { v4:5.w = vadd(v1:0.w,v3:2.w)
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# CHECK-NEXT: 2820c022 vmem(r0+#0x0) = v5.new }

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