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mariusz-sikora-at-amdmariusz-sikora-at-amd
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[AMDGPU][GFX12] Add new v_permlane16 variants (#75475)
1 parent d63f54f commit 966416b

19 files changed

+1459
-5
lines changed

‎clang/include/clang/Basic/BuiltinsAMDGPU.def

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -410,6 +410,8 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts")
410410
// GFX12+ only builtins.
411411
//===----------------------------------------------------------------------===//
412412

413+
TARGET_BUILTIN(__builtin_amdgcn_permlane16_var, "UiUiUiUiIbIb", "nc", "gfx12-insts")
414+
TARGET_BUILTIN(__builtin_amdgcn_permlanex16_var, "UiUiUiUiIbIb", "nc", "gfx12-insts")
413415
TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal, "vIi", "n", "gfx12-insts")
414416
TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal_var, "vi", "n", "gfx12-insts")
415417
TARGET_BUILTIN(__builtin_amdgcn_s_barrier_wait, "vIs", "n", "gfx12-insts")

‎clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,54 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
22
// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -S -emit-llvm -o - %s | FileCheck %s
33

4+
// REQUIRES: amdgpu-registered-target
5+
6+
typedef unsigned int uint;
7+
8+
// CHECK-LABEL: @test_permlane16_var(
9+
// CHECK-NEXT: entry:
10+
// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5)
11+
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
12+
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
13+
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
14+
// CHECK-NEXT: store ptr addrspace(1) [[OUT:%.*]], ptr addrspace(5) [[OUT_ADDR]], align 8
15+
// CHECK-NEXT: store i32 [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 4
16+
// CHECK-NEXT: store i32 [[B:%.*]], ptr addrspace(5) [[B_ADDR]], align 4
17+
// CHECK-NEXT: store i32 [[C:%.*]], ptr addrspace(5) [[C_ADDR]], align 4
18+
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[A_ADDR]], align 4
19+
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[B_ADDR]], align 4
20+
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(5) [[C_ADDR]], align 4
21+
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.permlane16.var(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i1 false, i1 false)
22+
// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(1), ptr addrspace(5) [[OUT_ADDR]], align 8
23+
// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(1) [[TMP4]], align 4
24+
// CHECK-NEXT: ret void
25+
//
26+
void test_permlane16_var(global uint* out, uint a, uint b, uint c) {
27+
*out = __builtin_amdgcn_permlane16_var(a, b, c, 0, 0);
28+
}
29+
30+
// CHECK-LABEL: @test_permlanex16_var(
31+
// CHECK-NEXT: entry:
32+
// CHECK-NEXT: [[OUT_ADDR:%.*]] = alloca ptr addrspace(1), align 8, addrspace(5)
33+
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
34+
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
35+
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
36+
// CHECK-NEXT: store ptr addrspace(1) [[OUT:%.*]], ptr addrspace(5) [[OUT_ADDR]], align 8
37+
// CHECK-NEXT: store i32 [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 4
38+
// CHECK-NEXT: store i32 [[B:%.*]], ptr addrspace(5) [[B_ADDR]], align 4
39+
// CHECK-NEXT: store i32 [[C:%.*]], ptr addrspace(5) [[C_ADDR]], align 4
40+
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[A_ADDR]], align 4
41+
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[B_ADDR]], align 4
42+
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(5) [[C_ADDR]], align 4
43+
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.permlanex16.var(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i1 false, i1 false)
44+
// CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(1), ptr addrspace(5) [[OUT_ADDR]], align 8
45+
// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(1) [[TMP4]], align 4
46+
// CHECK-NEXT: ret void
47+
//
48+
void test_permlanex16_var(global uint* out, uint a, uint b, uint c) {
49+
*out = __builtin_amdgcn_permlanex16_var(a, b, c, 0, 0);
50+
}
51+
452
// CHECK-LABEL: @test_s_barrier_signal(
553
// CHECK-NEXT: entry:
654
// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)

‎clang/test/SemaOpenCL/builtins-amdgcn-error-gfx12-param.cl

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
// REQUIRES: amdgpu-registered-target
2+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx1200 -verify -S -o - %s
3+
4+
typedef unsigned int uint;
5+
6+
void test_permlane16_var(global uint* out, uint a, uint b, uint c, uint d) {
7+
*out = __builtin_amdgcn_permlane16_var(a, b, c, d, 1); // expected-error{{argument to '__builtin_amdgcn_permlane16_var' must be a constant integer}}
8+
*out = __builtin_amdgcn_permlane16_var(a, b, c, 1, d); // expected-error{{argument to '__builtin_amdgcn_permlane16_var' must be a constant integer}}
9+
}
10+
11+
void test_permlanex16_var(global uint* out, uint a, uint b, uint c, uint d) {
12+
*out = __builtin_amdgcn_permlanex16_var(a, b, c, d, 1); // expected-error{{argument to '__builtin_amdgcn_permlanex16_var' must be a constant integer}}
13+
*out = __builtin_amdgcn_permlanex16_var(a, b, c, 1, d); // expected-error{{argument to '__builtin_amdgcn_permlanex16_var' must be a constant integer}}
14+
}

‎clang/test/SemaOpenCL/builtins-amdgcn-error-gfx12.cl

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
// REQUIRES: amdgpu-registered-target
2+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu tahiti -verify -S -o - %s
3+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu hawaii -verify -S -o - %s
4+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu fiji -verify -S -o - %s
5+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx900 -verify -S -o - %s
6+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx908 -verify -S -o - %s
7+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx1010 -verify -S -o - %s
8+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx1030 -verify -S -o - %s
9+
// RUN: %clang_cc1 -triple amdgcn-- -target-cpu gfx1100 -verify -S -o - %s
10+
11+
typedef unsigned int uint;
12+
13+
void test(global uint* out, uint a, uint b, uint c) {
14+
*out = __builtin_amdgcn_permlane16_var(a, b, c, 1, 1); // expected-error {{'__builtin_amdgcn_permlane16_var' needs target feature gfx12-insts}}
15+
*out = __builtin_amdgcn_permlanex16_var(a, b, c, 1, 1); // expected-error {{'__builtin_amdgcn_permlanex16_var' needs target feature gfx12-insts}}
16+
}

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2466,6 +2466,24 @@ def int_amdgcn_s_wait_event_export_ready :
24662466
Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn]
24672467
>;
24682468

2469+
//===----------------------------------------------------------------------===//
2470+
// GFX12 Intrinsics
2471+
//===----------------------------------------------------------------------===//
2472+
2473+
// llvm.amdgcn.permlane16.var <old> <src0> <src1> <fi> <bound_control>
2474+
def int_amdgcn_permlane16_var : ClangBuiltin<"__builtin_amdgcn_permlane16_var">,
2475+
Intrinsic<[llvm_i32_ty],
2476+
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty],
2477+
[IntrNoMem, IntrConvergent, IntrWillReturn,
2478+
ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, IntrNoCallback, IntrNoFree]>;
2479+
2480+
// llvm.amdgcn.permlanex16.var <old> <src0> <src1> <fi> <bound_control>
2481+
def int_amdgcn_permlanex16_var : ClangBuiltin<"__builtin_amdgcn_permlanex16_var">,
2482+
Intrinsic<[llvm_i32_ty],
2483+
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty],
2484+
[IntrNoMem, IntrConvergent, IntrWillReturn,
2485+
ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, IntrNoCallback, IntrNoFree]>;
2486+
24692487
//===----------------------------------------------------------------------===//
24702488
// Deep learning intrinsics.
24712489
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -992,14 +992,27 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
992992
return IC.replaceOperand(II, 0, UndefValue::get(Old->getType()));
993993
}
994994
case Intrinsic::amdgcn_permlane16:
995-
case Intrinsic::amdgcn_permlanex16: {
995+
case Intrinsic::amdgcn_permlane16_var:
996+
case Intrinsic::amdgcn_permlanex16:
997+
case Intrinsic::amdgcn_permlanex16_var: {
996998
// Discard vdst_in if it's not going to be read.
997999
Value *VDstIn = II.getArgOperand(0);
9981000
if (isa<UndefValue>(VDstIn))
9991001
break;
10001002

1001-
ConstantInt *FetchInvalid = cast<ConstantInt>(II.getArgOperand(4));
1002-
ConstantInt *BoundCtrl = cast<ConstantInt>(II.getArgOperand(5));
1003+
// FetchInvalid operand idx.
1004+
unsigned int FiIdx = (IID == Intrinsic::amdgcn_permlane16 ||
1005+
IID == Intrinsic::amdgcn_permlanex16)
1006+
? 4 /* for permlane16 and permlanex16 */
1007+
: 3; /* for permlane16_var and permlanex16_var */
1008+
1009+
// BoundCtrl operand idx.
1010+
// For permlane16 and permlanex16 it should be 5
1011+
// For Permlane16_var and permlanex16_var it should be 4
1012+
unsigned int BcIdx = FiIdx + 1;
1013+
1014+
ConstantInt *FetchInvalid = cast<ConstantInt>(II.getArgOperand(FiIdx));
1015+
ConstantInt *BoundCtrl = cast<ConstantInt>(II.getArgOperand(BcIdx));
10031016
if (!FetchInvalid->getZExtValue() && !BoundCtrl->getZExtValue())
10041017
break;
10051018

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4439,6 +4439,15 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
44394439
OpdsMapping[5] = getSGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
44404440
break;
44414441
}
4442+
case Intrinsic::amdgcn_permlane16_var:
4443+
case Intrinsic::amdgcn_permlanex16_var: {
4444+
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
4445+
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
4446+
OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
4447+
OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
4448+
OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
4449+
break;
4450+
}
44424451
case Intrinsic::amdgcn_mfma_f32_4x4x1f32:
44434452
case Intrinsic::amdgcn_mfma_f32_4x4x4f16:
44444453
case Intrinsic::amdgcn_mfma_i32_4x4x4i8:

‎llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td

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Original file line numberDiff line numberDiff line change
@@ -333,6 +333,8 @@ def : SourceOfDivergence<int_amdgcn_ds_ordered_add>;
333333
def : SourceOfDivergence<int_amdgcn_ds_ordered_swap>;
334334
def : SourceOfDivergence<int_amdgcn_permlane16>;
335335
def : SourceOfDivergence<int_amdgcn_permlanex16>;
336+
def : SourceOfDivergence<int_amdgcn_permlane16_var>;
337+
def : SourceOfDivergence<int_amdgcn_permlanex16_var>;
336338
def : SourceOfDivergence<int_amdgcn_mov_dpp>;
337339
def : SourceOfDivergence<int_amdgcn_mov_dpp8>;
338340
def : SourceOfDivergence<int_amdgcn_update_dpp>;

‎llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,9 @@ static bool isSendMsgTraceDataOrGDS(const SIInstrInfo &TII,
163163
static bool isPermlane(const MachineInstr &MI) {
164164
unsigned Opcode = MI.getOpcode();
165165
return Opcode == AMDGPU::V_PERMLANE16_B32_e64 ||
166-
Opcode == AMDGPU::V_PERMLANEX16_B32_e64;
166+
Opcode == AMDGPU::V_PERMLANEX16_B32_e64 ||
167+
Opcode == AMDGPU::V_PERMLANE16_VAR_B32_e64 ||
168+
Opcode == AMDGPU::V_PERMLANEX16_VAR_B32_e64;
167169
}
168170

169171
static bool isLdsDma(const MachineInstr &MI) {

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -498,7 +498,9 @@ bool isPermlane16(unsigned Opc) {
498498
Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
499499
Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
500500
Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
501-
Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12;
501+
Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
502+
Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
503+
Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
502504
}
503505

504506
bool isGenericAtomic(unsigned Opc) {

‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -735,6 +735,15 @@ def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3
735735
let HasExtDPP = 0;
736736
}
737737

738+
def VOP3_PERMLANE_VAR_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, untyped]>, VOP3_OPSEL> {
739+
let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
740+
IntOpSelMods:$src1_modifiers, VRegSrc_32:$src1,
741+
VGPR_32:$vdst_in, op_sel0:$op_sel);
742+
let HasClamp = 0;
743+
let HasExtVOP3DPP = 0;
744+
let HasExtDPP = 0;
745+
}
746+
738747
def opsel_i1timm : SDNodeXForm<timm, [{
739748
return CurDAG->getTargetConstant(
740749
N->getZExtValue() ? SISrcMods::OP_SEL_0 : SISrcMods::NONE,
@@ -751,6 +760,13 @@ class PermlanePat<SDPatternOperator permlane,
751760
SCSrc_b32:$src1, 0, SCSrc_b32:$src2, VGPR_32:$vdst_in)
752761
>;
753762

763+
class PermlaneVarPat<SDPatternOperator permlane,
764+
Instruction inst> : GCNPat<
765+
(permlane i32:$vdst_in, i32:$src0, i32:$src1,
766+
timm:$fi, timm:$bc),
767+
(inst (opsel_i1timm $fi), VGPR_32:$src0, (opsel_i1timm $bc),
768+
VGPR_32:$src1, VGPR_32:$vdst_in)
769+
>;
754770

755771
let SubtargetPredicate = isGFX10Plus in {
756772
let isCommutable = 1, isReMaterializable = 1 in {
@@ -781,6 +797,17 @@ let SubtargetPredicate = isGFX10Plus in {
781797

782798
} // End SubtargetPredicate = isGFX10Plus
783799

800+
let SubtargetPredicate = isGFX12Plus in {
801+
let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
802+
defm V_PERMLANE16_VAR_B32 : VOP3Inst<"v_permlane16_var_b32", VOP3_PERMLANE_VAR_Profile>;
803+
defm V_PERMLANEX16_VAR_B32 : VOP3Inst<"v_permlanex16_var_b32", VOP3_PERMLANE_VAR_Profile>;
804+
} // End $vdst = $vdst_in, DisableEncoding $vdst_in
805+
806+
def : PermlaneVarPat<int_amdgcn_permlane16_var, V_PERMLANE16_VAR_B32_e64>;
807+
def : PermlaneVarPat<int_amdgcn_permlanex16_var, V_PERMLANEX16_VAR_B32_e64>;
808+
809+
} // End SubtargetPredicate = isGFX12Plus
810+
784811
class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
785812
(AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
786813
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)),
@@ -915,6 +942,9 @@ defm V_MAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x366>;
915942
defm V_MINIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x367>;
916943
defm V_MAXIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x368>;
917944

945+
defm V_PERMLANE16_VAR_B32 : VOP3Only_Real_Base_gfx12<0x30f>;
946+
defm V_PERMLANEX16_VAR_B32 : VOP3Only_Real_Base_gfx12<0x310>;
947+
918948
//===----------------------------------------------------------------------===//
919949
// GFX11, GFX12
920950
//===----------------------------------------------------------------------===//

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,20 @@ define amdgpu_kernel void @v_permlanex16_b32(ptr addrspace(1) %out, i32 %src0, i
2121
ret void
2222
}
2323

24+
; CHECK: DIVERGENT: %v = call i32 @llvm.amdgcn.permlane16.var(i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0
25+
define amdgpu_kernel void @v_permlane16_var_b32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
26+
%v = call i32 @llvm.amdgcn.permlane16.var(i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0
27+
store i32 %v, ptr addrspace(1) %out
28+
ret void
29+
}
30+
31+
; CHECK: DIVERGENT: %v = call i32 @llvm.amdgcn.permlanex16.var(i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0
32+
define amdgpu_kernel void @v_permlanex16_var_b32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
33+
%v = call i32 @llvm.amdgcn.permlanex16.var(i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0
34+
store i32 %v, ptr addrspace(1) %out
35+
ret void
36+
}
37+
2438
; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0
2539
define amdgpu_kernel void @update_dpp(ptr addrspace(1) %out, i32 %in1, i32 %in2) #0 {
2640
%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0
@@ -98,6 +112,8 @@ bb:
98112
declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #1
99113
declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1) #1
100114
declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1) #1
115+
declare i32 @llvm.amdgcn.permlane16.var(i32, i32, i32, i1, i1) #1
116+
declare i32 @llvm.amdgcn.permlanex16.var(i32, i32, i32, i1, i1) #1
101117
declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #1
102118
declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #1
103119
declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #1

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