Skip to content

Commit 96c4f10

Browse files
tclin914tclin914
authored
[RISCV] Add support predicating for ANDN/ORN/XNOR with short-forward-branch-opt. (#77077)
ANDN/ORN/XNOR are like other ALU instructions. It should be able to be predicated by the cpu that supports short-forward-branch.
1 parent af1fdcc commit 96c4f10

File tree

4 files changed

+179
-10
lines changed

4 files changed

+179
-10
lines changed

‎llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,9 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
135135
case RISCV::PseudoCCSLLIW:
136136
case RISCV::PseudoCCSRLIW:
137137
case RISCV::PseudoCCSRAIW:
138+
case RISCV::PseudoCCANDN:
139+
case RISCV::PseudoCCORN:
140+
case RISCV::PseudoCCXNOR:
138141
return expandCCOp(MBB, MBBI, NextMBBI);
139142
case RISCV::PseudoVSETVLI:
140143
case RISCV::PseudoVSETVLIX0:
@@ -227,6 +230,9 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
227230
case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
228231
case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
229232
case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
233+
case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
234+
case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
235+
case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
230236
}
231237
BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
232238
.add(MI.getOperand(5))

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1346,6 +1346,10 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
13461346
case RISCV::SLLIW: return RISCV::PseudoCCSLLIW; break;
13471347
case RISCV::SRLIW: return RISCV::PseudoCCSRLIW; break;
13481348
case RISCV::SRAIW: return RISCV::PseudoCCSRAIW; break;
1349+
1350+
case RISCV::ANDN: return RISCV::PseudoCCANDN; break;
1351+
case RISCV::ORN: return RISCV::PseudoCCORN; break;
1352+
case RISCV::XNOR: return RISCV::PseudoCCXNOR; break;
13491353
}
13501354

13511355
return RISCV::INSTRUCTION_LIST_END;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1519,6 +1519,23 @@ def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
15191519
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
15201520
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
15211521
ReadSFBALU]>;
1522+
1523+
// Zbb/Zbkb instructions
1524+
def PseudoCCANDN : Pseudo<(outs GPR:$dst),
1525+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1526+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1527+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1528+
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1529+
def PseudoCCORN : Pseudo<(outs GPR:$dst),
1530+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1531+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1532+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1533+
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
1534+
def PseudoCCXNOR : Pseudo<(outs GPR:$dst),
1535+
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1536+
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
1537+
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
1538+
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
15221539
}
15231540

15241541
multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {

‎llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll

Lines changed: 152 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs < %s \
2+
; RUN: llc -mtriple=riscv64 -mattr=+c,+zbb -verify-machineinstrs < %s \
33
; RUN: | FileCheck -check-prefix=NOSFB %s
4-
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s \
4+
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+zbb -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV64SFB %s
6-
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond \
6+
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -mattr=+experimental-zicond,+zbb \
77
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=SFB,ZICOND %s
8-
; RUN: llc -mtriple=riscv32 -mcpu=sifive-e76 -verify-machineinstrs < %s \
8+
; RUN: llc -mtriple=riscv32 -mcpu=sifive-e76 -mattr=+zbb -verify-machineinstrs < %s \
99
; RUN: | FileCheck -check-prefixes=SFB,NOZICOND,RV32SFB %s
1010

1111
; The sifive-7-series can predicate a mv.
@@ -1462,9 +1462,8 @@ entry:
14621462
define signext i32 @abs_i32(i32 signext %x) {
14631463
; NOSFB-LABEL: abs_i32:
14641464
; NOSFB: # %bb.0:
1465-
; NOSFB-NEXT: sraiw a1, a0, 31
1466-
; NOSFB-NEXT: xor a0, a0, a1
1467-
; NOSFB-NEXT: subw a0, a0, a1
1465+
; NOSFB-NEXT: negw a1, a0
1466+
; NOSFB-NEXT: max a0, a0, a1
14681467
; NOSFB-NEXT: ret
14691468
;
14701469
; RV64SFB-LABEL: abs_i32:
@@ -1498,9 +1497,8 @@ declare i32 @llvm.abs.i32(i32, i1)
14981497
define i64 @abs_i64(i64 %x) {
14991498
; NOSFB-LABEL: abs_i64:
15001499
; NOSFB: # %bb.0:
1501-
; NOSFB-NEXT: srai a1, a0, 63
1502-
; NOSFB-NEXT: xor a0, a0, a1
1503-
; NOSFB-NEXT: sub a0, a0, a1
1500+
; NOSFB-NEXT: neg a1, a0
1501+
; NOSFB-NEXT: max a0, a0, a1
15041502
; NOSFB-NEXT: ret
15051503
;
15061504
; RV64SFB-LABEL: abs_i64:
@@ -1536,3 +1534,147 @@ define i64 @abs_i64(i64 %x) {
15361534
ret i64 %a
15371535
}
15381536
declare i64 @llvm.abs.i64(i64, i1)
1537+
1538+
define i64 @select_andn(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) {
1539+
; NOSFB-LABEL: select_andn:
1540+
; NOSFB: # %bb.0: # %entry
1541+
; NOSFB-NEXT: bnez a3, .LBB36_2
1542+
; NOSFB-NEXT: # %bb.1: # %entry
1543+
; NOSFB-NEXT: andn a2, a0, a1
1544+
; NOSFB-NEXT: .LBB36_2: # %entry
1545+
; NOSFB-NEXT: mv a0, a2
1546+
; NOSFB-NEXT: ret
1547+
;
1548+
; RV64SFB-LABEL: select_andn:
1549+
; RV64SFB: # %bb.0: # %entry
1550+
; RV64SFB-NEXT: bnez a3, .LBB36_2
1551+
; RV64SFB-NEXT: # %bb.1: # %entry
1552+
; RV64SFB-NEXT: andn a2, a0, a1
1553+
; RV64SFB-NEXT: .LBB36_2: # %entry
1554+
; RV64SFB-NEXT: mv a0, a2
1555+
; RV64SFB-NEXT: ret
1556+
;
1557+
; ZICOND-LABEL: select_andn:
1558+
; ZICOND: # %bb.0: # %entry
1559+
; ZICOND-NEXT: bnez a3, .LBB36_2
1560+
; ZICOND-NEXT: # %bb.1: # %entry
1561+
; ZICOND-NEXT: andn a2, a0, a1
1562+
; ZICOND-NEXT: .LBB36_2: # %entry
1563+
; ZICOND-NEXT: mv a0, a2
1564+
; ZICOND-NEXT: ret
1565+
;
1566+
; RV32SFB-LABEL: select_andn:
1567+
; RV32SFB: # %bb.0: # %entry
1568+
; RV32SFB-NEXT: bnez a6, .LBB36_2
1569+
; RV32SFB-NEXT: # %bb.1: # %entry
1570+
; RV32SFB-NEXT: andn a4, a0, a2
1571+
; RV32SFB-NEXT: .LBB36_2: # %entry
1572+
; RV32SFB-NEXT: bnez a6, .LBB36_4
1573+
; RV32SFB-NEXT: # %bb.3: # %entry
1574+
; RV32SFB-NEXT: andn a5, a1, a3
1575+
; RV32SFB-NEXT: .LBB36_4: # %entry
1576+
; RV32SFB-NEXT: mv a0, a4
1577+
; RV32SFB-NEXT: mv a1, a5
1578+
; RV32SFB-NEXT: ret
1579+
entry:
1580+
%0 = xor i64 %B, -1
1581+
%1 = and i64 %A, %0
1582+
%2 = select i1 %cond, i64 %C, i64 %1
1583+
ret i64 %2
1584+
}
1585+
1586+
define i64 @select_orn(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) {
1587+
; NOSFB-LABEL: select_orn:
1588+
; NOSFB: # %bb.0: # %entry
1589+
; NOSFB-NEXT: bnez a3, .LBB37_2
1590+
; NOSFB-NEXT: # %bb.1: # %entry
1591+
; NOSFB-NEXT: orn a2, a0, a1
1592+
; NOSFB-NEXT: .LBB37_2: # %entry
1593+
; NOSFB-NEXT: mv a0, a2
1594+
; NOSFB-NEXT: ret
1595+
;
1596+
; RV64SFB-LABEL: select_orn:
1597+
; RV64SFB: # %bb.0: # %entry
1598+
; RV64SFB-NEXT: bnez a3, .LBB37_2
1599+
; RV64SFB-NEXT: # %bb.1: # %entry
1600+
; RV64SFB-NEXT: orn a2, a0, a1
1601+
; RV64SFB-NEXT: .LBB37_2: # %entry
1602+
; RV64SFB-NEXT: mv a0, a2
1603+
; RV64SFB-NEXT: ret
1604+
;
1605+
; ZICOND-LABEL: select_orn:
1606+
; ZICOND: # %bb.0: # %entry
1607+
; ZICOND-NEXT: bnez a3, .LBB37_2
1608+
; ZICOND-NEXT: # %bb.1: # %entry
1609+
; ZICOND-NEXT: orn a2, a0, a1
1610+
; ZICOND-NEXT: .LBB37_2: # %entry
1611+
; ZICOND-NEXT: mv a0, a2
1612+
; ZICOND-NEXT: ret
1613+
;
1614+
; RV32SFB-LABEL: select_orn:
1615+
; RV32SFB: # %bb.0: # %entry
1616+
; RV32SFB-NEXT: bnez a6, .LBB37_2
1617+
; RV32SFB-NEXT: # %bb.1: # %entry
1618+
; RV32SFB-NEXT: orn a4, a0, a2
1619+
; RV32SFB-NEXT: .LBB37_2: # %entry
1620+
; RV32SFB-NEXT: bnez a6, .LBB37_4
1621+
; RV32SFB-NEXT: # %bb.3: # %entry
1622+
; RV32SFB-NEXT: orn a5, a1, a3
1623+
; RV32SFB-NEXT: .LBB37_4: # %entry
1624+
; RV32SFB-NEXT: mv a0, a4
1625+
; RV32SFB-NEXT: mv a1, a5
1626+
; RV32SFB-NEXT: ret
1627+
entry:
1628+
%0 = xor i64 %B, -1
1629+
%1 = or i64 %A, %0
1630+
%2 = select i1 %cond, i64 %C, i64 %1
1631+
ret i64 %2
1632+
}
1633+
1634+
define i64 @select_xnor(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) {
1635+
; NOSFB-LABEL: select_xnor:
1636+
; NOSFB: # %bb.0: # %entry
1637+
; NOSFB-NEXT: bnez a3, .LBB38_2
1638+
; NOSFB-NEXT: # %bb.1: # %entry
1639+
; NOSFB-NEXT: xnor a2, a0, a1
1640+
; NOSFB-NEXT: .LBB38_2: # %entry
1641+
; NOSFB-NEXT: mv a0, a2
1642+
; NOSFB-NEXT: ret
1643+
;
1644+
; RV64SFB-LABEL: select_xnor:
1645+
; RV64SFB: # %bb.0: # %entry
1646+
; RV64SFB-NEXT: bnez a3, .LBB38_2
1647+
; RV64SFB-NEXT: # %bb.1: # %entry
1648+
; RV64SFB-NEXT: xnor a2, a0, a1
1649+
; RV64SFB-NEXT: .LBB38_2: # %entry
1650+
; RV64SFB-NEXT: mv a0, a2
1651+
; RV64SFB-NEXT: ret
1652+
;
1653+
; ZICOND-LABEL: select_xnor:
1654+
; ZICOND: # %bb.0: # %entry
1655+
; ZICOND-NEXT: bnez a3, .LBB38_2
1656+
; ZICOND-NEXT: # %bb.1: # %entry
1657+
; ZICOND-NEXT: xnor a2, a0, a1
1658+
; ZICOND-NEXT: .LBB38_2: # %entry
1659+
; ZICOND-NEXT: mv a0, a2
1660+
; ZICOND-NEXT: ret
1661+
;
1662+
; RV32SFB-LABEL: select_xnor:
1663+
; RV32SFB: # %bb.0: # %entry
1664+
; RV32SFB-NEXT: bnez a6, .LBB38_2
1665+
; RV32SFB-NEXT: # %bb.1: # %entry
1666+
; RV32SFB-NEXT: xnor a4, a0, a2
1667+
; RV32SFB-NEXT: .LBB38_2: # %entry
1668+
; RV32SFB-NEXT: bnez a6, .LBB38_4
1669+
; RV32SFB-NEXT: # %bb.3: # %entry
1670+
; RV32SFB-NEXT: xnor a5, a1, a3
1671+
; RV32SFB-NEXT: .LBB38_4: # %entry
1672+
; RV32SFB-NEXT: mv a0, a4
1673+
; RV32SFB-NEXT: mv a1, a5
1674+
; RV32SFB-NEXT: ret
1675+
entry:
1676+
%0 = xor i64 %A, %B
1677+
%1 = xor i64 %0, -1
1678+
%2 = select i1 %cond, i64 %C, i64 %1
1679+
ret i64 %2
1680+
}

0 commit comments

Comments
 (0)